#include <rte_memzone.h>
#include <rte_dev.h>
-#include "iavf_log.h"
-#include "base/iavf_prototype.h"
-#include "base/iavf_adminq_cmd.h"
-#include "base/iavf_type.h"
-
#include "iavf.h"
#include "iavf_rxtx.h"
ad->rx_vec_allowed = true;
ad->tx_vec_allowed = true;
+ if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
+ dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
+
/* Vlan stripping setting */
if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN) {
if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
/* If WB_ON_ITR supports, enable it */
vf->msix_base = IAVF_RX_VEC_START;
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTLN1(vf->msix_base - 1),
- IAVFINT_DYN_CTLN1_ITR_INDX_MASK |
- IAVFINT_DYN_CTLN1_WB_ON_ITR_MASK);
+ IAVF_WRITE_REG(hw,
+ IAVF_VFINT_DYN_CTLN1(vf->msix_base - 1),
+ IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |
+ IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
} else {
/* If no WB_ON_ITR offload flags, need to set
* interrupt for descriptor write back.
/* set ITR to max */
interval = iavf_calc_itr_interval(
IAVF_QUEUE_ITR_INTERVAL_MAX);
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
- IAVFINT_DYN_CTL01_INTENA_MASK |
- (IAVF_ITR_INDEX_DEFAULT <<
- IAVFINT_DYN_CTL01_ITR_INDX_SHIFT) |
- (interval <<
- IAVFINT_DYN_CTL01_INTERVAL_SHIFT));
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_INTENA_MASK |
+ (IAVF_ITR_INDEX_DEFAULT <<
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
+ (interval <<
+ IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));
}
IAVF_WRITE_FLUSH(hw);
/* map all queues to the same interrupt */
struct iavf_adapter *adapter =
IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
- struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_intr_handle *intr_handle = dev->intr_handle;
PMD_INIT_FUNC_TRACE();
- hw->adapter_stopped = 0;
+ adapter->stopped = 0;
vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
{
struct iavf_adapter *adapter =
IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
- struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_intr_handle *intr_handle = dev->intr_handle;
PMD_INIT_FUNC_TRACE();
- if (hw->adapter_stopped == 1)
+ if (adapter->stopped == 1)
return;
iavf_stop_queues(dev);
/* remove all mac addrs */
iavf_add_del_all_mac_addr(adapter, FALSE);
- hw->adapter_stopped = 1;
+ adapter->stopped = 1;
}
static int
DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
DEV_RX_OFFLOAD_SCATTER |
DEV_RX_OFFLOAD_JUMBO_FRAME |
- DEV_RX_OFFLOAD_VLAN_FILTER;
+ DEV_RX_OFFLOAD_VLAN_FILTER |
+ DEV_RX_OFFLOAD_RSS_HASH;
dev_info->tx_offload_capa =
DEV_TX_OFFLOAD_VLAN_INSERT |
DEV_TX_OFFLOAD_QINQ_INSERT |
if (ret == 0) {
iavf_update_stats(vsi, pstats);
stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
- pstats->rx_broadcast;
+ pstats->rx_broadcast - pstats->rx_discards;
stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
pstats->tx_unicast;
stats->imissed = pstats->rx_discards;
msix_intr = pci_dev->intr_handle.intr_vec[queue_id];
if (msix_intr == IAVF_MISC_VEC_ID) {
PMD_DRV_LOG(INFO, "MISC is also enabled for control");
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
- IAVFINT_DYN_CTL01_INTENA_MASK |
- IAVFINT_DYN_CTL01_CLEARPBA_MASK |
- IAVFINT_DYN_CTL01_ITR_INDX_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_INTENA_MASK |
+ IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
} else {
IAVF_WRITE_REG(hw,
- IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
- IAVFINT_DYN_CTLN1_INTENA_MASK |
- IAVFINT_DYN_CTL01_CLEARPBA_MASK |
- IAVFINT_DYN_CTLN1_ITR_INDX_MASK);
+ IAVF_VFINT_DYN_CTLN1
+ (msix_intr - IAVF_RX_VEC_START),
+ IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
+ IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
+ IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK);
}
IAVF_WRITE_FLUSH(hw);
}
IAVF_WRITE_REG(hw,
- IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
+ IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
0);
IAVF_WRITE_FLUSH(hw);
int i, reset;
for (i = 0; i < IAVF_RESET_WAIT_CNT; i++) {
- reset = IAVF_READ_REG(hw, IAVFGEN_RSTAT) &
- IAVFGEN_RSTAT_VFR_STATE_MASK;
- reset = reset >> IAVFGEN_RSTAT_VFR_STATE_SHIFT;
+ reset = IAVF_READ_REG(hw, IAVF_VFGEN_RSTAT) &
+ IAVF_VFGEN_RSTAT_VFR_STATE_MASK;
+ reset = reset >> IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT;
if (reset == VIRTCHNL_VFR_VFACTIVE ||
reset == VIRTCHNL_VFR_COMPLETED)
break;
iavf_enable_irq0(struct iavf_hw *hw)
{
/* Enable admin queue interrupt trigger */
- IAVF_WRITE_REG(hw, IAVFINT_ICR0_ENA1, IAVFINT_ICR0_ENA1_ADMINQ_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_ICR0_ENA1,
+ IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK);
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01, IAVFINT_DYN_CTL01_INTENA_MASK |
- IAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTL01_ITR_INDX_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_INTENA_MASK |
+ IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
IAVF_WRITE_FLUSH(hw);
}
iavf_disable_irq0(struct iavf_hw *hw)
{
/* Disable all interrupt types */
- IAVF_WRITE_REG(hw, IAVFINT_ICR0_ENA1, 0);
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
- IAVFINT_DYN_CTL01_ITR_INDX_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_ICR0_ENA1, 0);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
IAVF_WRITE_FLUSH(hw);
}
hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
hw->back = IAVF_DEV_PRIVATE_TO_ADAPTER(eth_dev->data->dev_private);
adapter->eth_dev = eth_dev;
+ adapter->stopped = 1;
if (iavf_init_vf(eth_dev) != 0) {
PMD_INIT_LOG(ERR, "Init vf failed");
iavf_dev_uninit(struct rte_eth_dev *dev)
{
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
- struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return -EPERM;
dev->dev_ops = NULL;
dev->rx_pkt_burst = NULL;
dev->tx_pkt_burst = NULL;
- if (hw->adapter_stopped == 0)
- iavf_dev_close(dev);
+ iavf_dev_close(dev);
rte_free(vf->vf_res);
vf->vsi_res = NULL;
rte_log_set_level(iavf_logtype_tx_free, RTE_LOG_DEBUG);
#endif
}
-
-/* memory func for base code */
-enum iavf_status_code
-iavf_allocate_dma_mem_d(__rte_unused struct iavf_hw *hw,
- struct iavf_dma_mem *mem,
- u64 size,
- u32 alignment)
-{
- const struct rte_memzone *mz = NULL;
- char z_name[RTE_MEMZONE_NAMESIZE];
-
- if (!mem)
- return IAVF_ERR_PARAM;
-
- snprintf(z_name, sizeof(z_name), "iavf_dma_%"PRIu64, rte_rand());
- mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
- RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
- if (!mz)
- return IAVF_ERR_NO_MEMORY;
-
- mem->size = size;
- mem->va = mz->addr;
- mem->pa = mz->phys_addr;
- mem->zone = (const void *)mz;
- PMD_DRV_LOG(DEBUG,
- "memzone %s allocated with physical address: %"PRIu64,
- mz->name, mem->pa);
-
- return IAVF_SUCCESS;
-}
-
-enum iavf_status_code
-iavf_free_dma_mem_d(__rte_unused struct iavf_hw *hw,
- struct iavf_dma_mem *mem)
-{
- if (!mem)
- return IAVF_ERR_PARAM;
-
- PMD_DRV_LOG(DEBUG,
- "memzone %s to be freed with physical address: %"PRIu64,
- ((const struct rte_memzone *)mem->zone)->name, mem->pa);
- rte_memzone_free((const struct rte_memzone *)mem->zone);
- mem->zone = NULL;
- mem->va = NULL;
- mem->pa = (u64)0;
-
- return IAVF_SUCCESS;
-}
-
-enum iavf_status_code
-iavf_allocate_virt_mem_d(__rte_unused struct iavf_hw *hw,
- struct iavf_virt_mem *mem,
- u32 size)
-{
- if (!mem)
- return IAVF_ERR_PARAM;
-
- mem->size = size;
- mem->va = rte_zmalloc("iavf", size, 0);
-
- if (mem->va)
- return IAVF_SUCCESS;
- else
- return IAVF_ERR_NO_MEMORY;
-}
-
-enum iavf_status_code
-iavf_free_virt_mem_d(__rte_unused struct iavf_hw *hw,
- struct iavf_virt_mem *mem)
-{
- if (!mem)
- return IAVF_ERR_PARAM;
-
- rte_free(mem->va);
- mem->va = NULL;
-
- return IAVF_SUCCESS;
-}
git.droids-corp.org / dpdk.git / blobdiff