net/iavf: fix crash in AVX512

[dpdk.git] / drivers / net / iavf / iavf_rxtx_vec_avx2.c

diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c
index cdb5139..f5646d6 100644 (file)
--- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c
+++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c
@@ -10,126 +10,10 @@
 #pragma GCC diagnostic ignored "-Wcast-qual"
 #endif
 
-static inline void
+static __rte_always_inline void
 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
 {
-       int i;
-       uint16_t rx_id;
-       volatile union iavf_rx_desc *rxdp;
-       struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
-
-       rxdp = rxq->rx_ring + rxq->rxrearm_start;
-
-       /* Pull 'n' more MBUFs into the software ring */
-       if (rte_mempool_get_bulk(rxq->mp,
-                                (void *)rxp,
-                                IAVF_RXQ_REARM_THRESH) < 0) {
-               if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
-                   rxq->nb_rx_desc) {
-                       __m128i dma_addr0;
-
-                       dma_addr0 = _mm_setzero_si128();
-                       for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
-                               rxp[i] = &rxq->fake_mbuf;
-                               _mm_store_si128((__m128i *)&rxdp[i].read,
-                                               dma_addr0);
-                       }
-               }
-               rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
-                       IAVF_RXQ_REARM_THRESH;
-               return;
-       }
-
-#ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
-       struct rte_mbuf *mb0, *mb1;
-       __m128i dma_addr0, dma_addr1;
-       __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
-                       RTE_PKTMBUF_HEADROOM);
-       /* Initialize the mbufs in vector, process 2 mbufs in one loop */
-       for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxp += 2) {
-               __m128i vaddr0, vaddr1;
-
-               mb0 = rxp[0];
-               mb1 = rxp[1];
-
-               /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
-               RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
-                               offsetof(struct rte_mbuf, buf_addr) + 8);
-               vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
-               vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
-
-               /* convert pa to dma_addr hdr/data */
-               dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
-               dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
-
-               /* add headroom to pa values */
-               dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
-               dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
-
-               /* flush desc with pa dma_addr */
-               _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
-               _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
-       }
-#else
-       struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
-       __m256i dma_addr0_1, dma_addr2_3;
-       __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
-       /* Initialize the mbufs in vector, process 4 mbufs in one loop */
-       for (i = 0; i < IAVF_RXQ_REARM_THRESH;
-                       i += 4, rxp += 4, rxdp += 4) {
-               __m128i vaddr0, vaddr1, vaddr2, vaddr3;
-               __m256i vaddr0_1, vaddr2_3;
-
-               mb0 = rxp[0];
-               mb1 = rxp[1];
-               mb2 = rxp[2];
-               mb3 = rxp[3];
-
-               /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
-               RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
-                               offsetof(struct rte_mbuf, buf_addr) + 8);
-               vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
-               vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
-               vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
-               vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
-
-               /**
-                * merge 0 & 1, by casting 0 to 256-bit and inserting 1
-                * into the high lanes. Similarly for 2 & 3
-                */
-               vaddr0_1 =
-                       _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
-                                               vaddr1, 1);
-               vaddr2_3 =
-                       _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
-                                               vaddr3, 1);
-
-               /* convert pa to dma_addr hdr/data */
-               dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
-               dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
-
-               /* add headroom to pa values */
-               dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
-               dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
-
-               /* flush desc with pa dma_addr */
-               _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
-               _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
-       }
-
-#endif
-
-       rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
-       if (rxq->rxrearm_start >= rxq->nb_rx_desc)
-               rxq->rxrearm_start = 0;
-
-       rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
-
-       rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
-                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
-
-       /* Update the tail pointer on the NIC */
-       IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
+       return iavf_rxq_rearm_common(rxq, false);
 }
 
 #define PKTLEN_SHIFT     10