net/ice/base: remove redundant empty lines

[dpdk.git] / drivers / net / ice / base / ice_lan_tx_rx.h

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index e77d4bf..a97c63c 100644 (file)
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -173,7 +173,6 @@ struct ice_fltr_desc {
                        (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
 #define ICE_FXD_FLTR_QW1_FDID_ZERO     0x0ULL
 
-
 enum ice_rx_desc_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_STATUS_DD_S                 = 0,
@@ -204,7 +203,6 @@ enum ice_rx_desc_status_bits {
 #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S
 #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)
 
-
 enum ice_rx_desc_fltstat_values {
        ICE_RX_DESC_FLTSTAT_NO_DATA     = 0,
        ICE_RX_DESC_FLTSTAT_RSV_FD_ID   = 1, /* 16byte desc? FD_ID : RSV */
@@ -212,7 +210,6 @@ enum ice_rx_desc_fltstat_values {
        ICE_RX_DESC_FLTSTAT_RSS_HASH    = 3,
 };
 
-
 #define ICE_RXD_QW1_ERROR_S    19
 #define ICE_RXD_QW1_ERROR_M            (0xFFUL << ICE_RXD_QW1_ERROR_S)
 
@@ -310,7 +307,6 @@ enum ice_rx_ptype_payload_layer {
        ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
 };
 
-
 #define ICE_RXD_QW1_LEN_PBUF_S 38
 #define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)
 
@@ -320,7 +316,6 @@ enum ice_rx_ptype_payload_layer {
 #define ICE_RXD_QW1_LEN_SPH_S  63
 #define ICE_RXD_QW1_LEN_SPH_M  BIT_ULL(ICE_RXD_QW1_LEN_SPH_S)
 
-
 enum ice_rx_desc_ext_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_EXT_STATUS_L2TAG2P_S        = 0,
@@ -331,7 +326,6 @@ enum ice_rx_desc_ext_status_bits {
        ICE_RX_DESC_EXT_STATUS_PELONGB_S        = 11,
 };
 
-
 enum ice_rx_desc_pe_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_PE_STATUS_QPID_S            = 0, /* 18 BITS */
@@ -352,7 +346,6 @@ enum ice_rx_desc_pe_status_bits {
 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M   \
                        (0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)
 
-
 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S    19
 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M    \
                        (0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)
@@ -840,7 +833,6 @@ enum ice_rx_flex_desc_exstat_bits {
        ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
 };
 
-
 #define ICE_RXQ_CTX_SIZE_DWORDS                8
 #define ICE_RXQ_CTX_SZ                 (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
@@ -1056,7 +1048,6 @@ enum ice_tx_ctx_desc_eipt_offload {
 #define ICE_TXD_CTX_QW0_L4T_CS_S       23
 #define ICE_TXD_CTX_QW0_L4T_CS_M       BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
 
-
 #define ICE_LAN_TXQ_MAX_QGRPS  127
 #define ICE_LAN_TXQ_MAX_QDIS   1023