net/ice/base: store NVM version in extracted format

[dpdk.git] / drivers / net / ice / base / ice_type.h

diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 00459bc..89d4764 100644 (file)
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -476,12 +476,20 @@ struct ice_fc_info {
        enum ice_fc_mode req_mode;      /* FC mode requested by caller */
 };
 
+/* Option ROM version information */
+struct ice_orom_info {
+       u8 major;                       /* Major version of OROM */
+       u8 patch;                       /* Patch version of OROM */
+       u16 build;                      /* Build version of OROM */
+};
+
 /* NVM Information */
 struct ice_nvm_info {
+       struct ice_orom_info orom;      /* Option ROM version info */
        u32 eetrack;                    /* NVM data version */
-       u32 oem_ver;                    /* OEM version info */
        u16 sr_words;                   /* Shadow RAM size in words */
-       u16 ver;                        /* dev starter version */
+       u8 major_ver;                   /* major version of dev starter */
+       u8 minor_ver;                   /* minor version of dev starter */
        u8 blank_nvm_mode;              /* is NVM empty (no FW present)*/
 };
 
@@ -991,7 +999,7 @@ enum ice_sw_fwd_act_type {
 #define ICE_SR_PBA_BLOCK_PTR                   0x16
 #define ICE_SR_BOOT_CFG_PTR                    0x132
 #define ICE_SR_NVM_WOL_CFG                     0x19
-#define ICE_NVM_OEM_VER_OFF                    0x02
+#define ICE_NVM_OROM_VER_OFF                   0x02
 #define ICE_SR_NVM_DEV_STARTER_VER             0x18
 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR      0x27
 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR      0x28
@@ -1005,12 +1013,12 @@ enum ice_sw_fwd_act_type {
 #define ICE_NVM_VER_HI_SHIFT                   12
 #define ICE_NVM_VER_HI_MASK                    (0xf << ICE_NVM_VER_HI_SHIFT)
 #define ICE_OEM_EETRACK_ID                     0xffffffff
-#define ICE_OEM_VER_PATCH_SHIFT                        0
-#define ICE_OEM_VER_PATCH_MASK         (0xff << ICE_OEM_VER_PATCH_SHIFT)
-#define ICE_OEM_VER_BUILD_SHIFT                        8
-#define ICE_OEM_VER_BUILD_MASK         (0xffff << ICE_OEM_VER_BUILD_SHIFT)
-#define ICE_OEM_VER_SHIFT                      24
-#define ICE_OEM_VER_MASK                       (0xff << ICE_OEM_VER_SHIFT)
+#define ICE_OROM_VER_PATCH_SHIFT               0
+#define ICE_OROM_VER_PATCH_MASK                (0xff << ICE_OROM_VER_PATCH_SHIFT)
+#define ICE_OROM_VER_BUILD_SHIFT               8
+#define ICE_OROM_VER_BUILD_MASK                (0xffff << ICE_OROM_VER_BUILD_SHIFT)
+#define ICE_OROM_VER_SHIFT                     24
+#define ICE_OROM_VER_MASK                      (0xff << ICE_OROM_VER_SHIFT)
 #define ICE_SR_VPD_PTR                         0x2F
 #define ICE_SR_PXE_SETUP_PTR                   0x30
 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR                0x31