remove repeated 'the' in the code
[dpdk.git] / drivers / net / ice / ice_ethdev.h
index b4bf651..2e3e45f 100644 (file)
@@ -6,6 +6,7 @@
 #define _ICE_ETHDEV_H_
 
 #include <rte_kvargs.h>
+#include <rte_time.h>
 
 #include <ethdev_driver.h>
 
 #include "base/ice_adminq_cmd.h"
 #include "base/ice_flow.h"
 
-#define ICE_VLAN_TAG_SIZE        4
-
 #define ICE_ADMINQ_LEN               32
 #define ICE_SBIOQ_LEN                32
 #define ICE_MAILBOXQ_LEN             32
+#define ICE_SBQ_LEN                  64
 #define ICE_ADMINQ_BUF_SZ            4096
 #define ICE_SBIOQ_BUF_SZ             4096
 #define ICE_MAILBOXQ_BUF_SZ          4096
                       ICE_FLAG_VF_MAC_BY_PF)
 
 #define ICE_RSS_OFFLOAD_ALL ( \
-       ETH_RSS_IPV4 | \
-       ETH_RSS_FRAG_IPV4 | \
-       ETH_RSS_NONFRAG_IPV4_TCP | \
-       ETH_RSS_NONFRAG_IPV4_UDP | \
-       ETH_RSS_NONFRAG_IPV4_SCTP | \
-       ETH_RSS_NONFRAG_IPV4_OTHER | \
-       ETH_RSS_IPV6 | \
-       ETH_RSS_FRAG_IPV6 | \
-       ETH_RSS_NONFRAG_IPV6_TCP | \
-       ETH_RSS_NONFRAG_IPV6_UDP | \
-       ETH_RSS_NONFRAG_IPV6_SCTP | \
-       ETH_RSS_NONFRAG_IPV6_OTHER | \
-       ETH_RSS_L2_PAYLOAD)
+       RTE_ETH_RSS_IPV4 | \
+       RTE_ETH_RSS_FRAG_IPV4 | \
+       RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
+       RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+       RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
+       RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
+       RTE_ETH_RSS_IPV6 | \
+       RTE_ETH_RSS_FRAG_IPV6 | \
+       RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
+       RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
+       RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
+       RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
+       RTE_ETH_RSS_L2_PAYLOAD)
 
 /**
  * The overhead from MTU to max frame size.
  * Considering QinQ packet, the VLAN tag needs to be counted twice.
  */
 #define ICE_ETH_OVERHEAD \
-       (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+       (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2)
 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
 
 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
 /* Max number of flexible descriptor rxdid */
 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64
 
+/* Per-channel register definitions */
+#define GLTSYN_AUX_OUT(_chan, _idx)     (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
+#define GLTSYN_CLKO(_chan, _idx)        (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
+#define GLTSYN_TGT_L(_chan, _idx)       (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
+#define GLTSYN_TGT_H(_chan, _idx)       (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
+
 /* DDP package type */
 enum ice_pkg_type {
        ICE_PKG_TYPE_UNKNOWN,
@@ -150,6 +156,12 @@ enum ice_pkg_type {
        ICE_PKG_TYPE_COMMS,
 };
 
+enum pps_type {
+       PPS_NONE,
+       PPS_PIN,
+       PPS_MAX,
+};
+
 struct ice_adapter;
 
 /**
@@ -230,7 +242,7 @@ struct ice_vsi {
         * needs to add, HW needs to know the layout that VSIs are organized.
         * Besides that, VSI isan element and can't switch packets, which needs
         * to add new component VEB to perform switching. So, a new VSI needs
-        * to specify the the uplink VSI (Parent VSI) before created. The
+        * to specify the uplink VSI (Parent VSI) before created. The
         * uplink VSI will check whether it had a VEB to switch packets. If no,
         * it will try to create one. Then, uplink VSI will move the new VSI
         * into its' sib_vsi_list to manage all the downlink VSI.
@@ -304,6 +316,11 @@ struct ice_fdir_filter_conf {
        uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */
        uint64_t input_set_i; /* only for tunnel inner fields */
        uint32_t mark_flag;
+
+       struct ice_parser_profile *prof;
+       bool parser_ena;
+       u8 *pkt_buf;
+       u8 pkt_len;
 };
 
 #define ICE_MAX_FDIR_FILTER_NUM                (1024 * 16)
@@ -458,15 +475,35 @@ struct ice_pf {
 };
 
 #define ICE_MAX_QUEUE_NUM  2048
+#define ICE_MAX_PIN_NUM   4
 
 /**
  * Cache devargs parse result.
  */
 struct ice_devargs {
+       int rx_low_latency;
        int safe_mode_support;
        uint8_t proto_xtr_dflt;
        int pipe_mode_support;
        uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
+       uint8_t pin_idx;
+       uint8_t pps_out_ena;
+};
+
+/**
+ * Structure to store fdir fv entry.
+ */
+struct ice_fdir_prof_info {
+       struct ice_parser_profile prof;
+       u64 fdir_actived_cnt;
+};
+
+/**
+ * Structure to store rss fv entry.
+ */
+struct ice_rss_prof_info {
+       struct ice_parser_profile prof;
+       bool symm;
 };
 
 /**
@@ -486,11 +523,20 @@ struct ice_adapter {
        struct ice_devargs devargs;
        enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
        uint16_t fdir_ref_cnt;
+       /* For PTP */
+       struct rte_timecounter systime_tc;
+       struct rte_timecounter rx_tstamp_tc;
+       struct rte_timecounter tx_tstamp_tc;
+       bool ptp_ena;
+       uint64_t time_hw;
+       struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS];
+       struct ice_rss_prof_info rss_prof_info[ICE_MAX_PTGS];
 #ifdef RTE_ARCH_X86
        bool rx_use_avx2;
        bool rx_use_avx512;
        bool tx_use_avx2;
        bool tx_use_avx512;
+       bool rx_vec_offload_support;
 #endif
 };