#define _ICE_ETHDEV_H_
#include <rte_kvargs.h>
+#include <rte_time.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include "base/ice_common.h"
#include "base/ice_adminq_cmd.h"
+#include "base/ice_flow.h"
#define ICE_VLAN_TAG_SIZE 4
#define ICE_ADMINQ_LEN 32
#define ICE_SBIOQ_LEN 32
#define ICE_MAILBOXQ_LEN 32
+#define ICE_SBQ_LEN 64
#define ICE_ADMINQ_BUF_SZ 4096
#define ICE_SBIOQ_BUF_SZ 4096
#define ICE_MAILBOXQ_BUF_SZ 4096
#define ICE_MAX_PKT_TYPE 1024
+/* DDP package search path */
+#define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
+#define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
+#define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
+#define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
+#define ICE_MAX_PKG_FILENAME_SIZE 256
+
+#define MAX_ACL_NORMAL_ENTRIES 256
+
/**
* vlan_id is a 12 bit number.
* The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
ICE_FLAG_VF_MAC_BY_PF)
#define ICE_RSS_OFFLOAD_ALL ( \
- ETH_RSS_FRAG_IPV4 | \
- ETH_RSS_NONFRAG_IPV4_TCP | \
- ETH_RSS_NONFRAG_IPV4_UDP | \
- ETH_RSS_NONFRAG_IPV4_SCTP | \
- ETH_RSS_NONFRAG_IPV4_OTHER | \
- ETH_RSS_FRAG_IPV6 | \
- ETH_RSS_NONFRAG_IPV6_TCP | \
- ETH_RSS_NONFRAG_IPV6_UDP | \
- ETH_RSS_NONFRAG_IPV6_SCTP | \
- ETH_RSS_NONFRAG_IPV6_OTHER | \
- ETH_RSS_L2_PAYLOAD)
+ RTE_ETH_RSS_IPV4 | \
+ RTE_ETH_RSS_FRAG_IPV4 | \
+ RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
+ RTE_ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_FRAG_IPV6 | \
+ RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
+ RTE_ETH_RSS_L2_PAYLOAD)
/**
* The overhead from MTU to max frame size.
*/
#define ICE_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+#define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
+
+#define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
+#define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
+
+/* Max number of flexible descriptor rxdid */
+#define ICE_FLEX_DESC_RXDID_MAX_NUM 64
+
+/* Per-channel register definitions */
+#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
+#define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
+#define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
+#define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
/* DDP package type */
enum ice_pkg_type {
ICE_PKG_TYPE_COMMS,
};
+enum pps_type {
+ PPS_NONE,
+ PPS_PIN,
+ PPS_MAX,
+};
+
struct ice_adapter;
/**
struct ice_mac_filter_info mac_info;
};
+struct ice_vlan {
+ uint16_t tpid;
+ uint16_t vid;
+};
+
+#define ICE_VLAN(tpid, vid) \
+ ((struct ice_vlan){ tpid, vid })
+
/**
* VLAN filter structure
*/
struct ice_vlan_filter_info {
- uint16_t vlan_id;
+ struct ice_vlan vlan;
};
TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
struct ice_eth_stats eth_stats_offset;
struct ice_eth_stats eth_stats;
bool offset_loaded;
+ uint64_t old_rx_bytes;
+ uint64_t old_tx_bytes;
+};
+
+enum proto_xtr_type {
+ PROTO_XTR_NONE,
+ PROTO_XTR_VLAN,
+ PROTO_XTR_IPV4,
+ PROTO_XTR_IPV6,
+ PROTO_XTR_IPV6_FLOW,
+ PROTO_XTR_TCP,
+ PROTO_XTR_IP_OFFSET,
+ PROTO_XTR_MAX /* The last one */
+};
+
+enum ice_fdir_tunnel_type {
+ ICE_FDIR_TUNNEL_TYPE_NONE = 0,
+ ICE_FDIR_TUNNEL_TYPE_VXLAN,
+ ICE_FDIR_TUNNEL_TYPE_GTPU,
+ ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
};
struct rte_flow;
struct ice_fdir_filter_conf {
struct ice_fdir_fltr input;
- uint64_t input_set;
+ enum ice_fdir_tunnel_type tunnel_type;
+
+ struct ice_fdir_counter *counter; /* flow specific counter context */
+ struct rte_flow_action_count act_count;
+
+ uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */
+ uint64_t input_set_i; /* only for tunnel inner fields */
+ uint32_t mark_flag;
+};
+
+#define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
+
+struct ice_fdir_fltr_pattern {
+ enum ice_fltr_ptype flow_type;
+
+ union {
+ struct ice_fdir_v4 v4;
+ struct ice_fdir_v6 v6;
+ } ip, mask;
+
+ struct ice_fdir_udp_gtp gtpu_data;
+ struct ice_fdir_udp_gtp gtpu_mask;
+
+ struct ice_fdir_extra ext_data;
+ struct ice_fdir_extra ext_mask;
+
+ enum ice_fdir_tunnel_type tunnel_type;
};
#define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
#define ICE_FDIR_COUNTERS_PER_BLOCK 256
#define ICE_FDIR_COUNTER_INDEX(base_idx) \
((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
+struct ice_fdir_counter_pool;
+
struct ice_fdir_counter {
TAILQ_ENTRY(ice_fdir_counter) next;
+ struct ice_fdir_counter_pool *pool;
uint8_t shared;
uint32_t ref_cnt;
uint32_t id;
struct ice_rx_queue *rxq;
void *prg_pkt; /* memory for fdir program packet */
uint64_t dma_addr; /* physic address of packet memory*/
+ const struct rte_memzone *mz;
struct ice_fdir_filter_conf conf;
+ struct ice_fdir_filter_conf **hash_map;
+ struct rte_hash *hash_table;
+
struct ice_fdir_counter_pool_container counter;
};
+#define ICE_HASH_GTPU_CTX_EH_IP 0
+#define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
+#define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
+#define ICE_HASH_GTPU_CTX_UP_IP 3
+#define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
+#define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
+#define ICE_HASH_GTPU_CTX_DW_IP 6
+#define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
+#define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
+#define ICE_HASH_GTPU_CTX_MAX 9
+
+struct ice_hash_gtpu_ctx {
+ struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
+};
+
+struct ice_hash_ctx {
+ struct ice_hash_gtpu_ctx gtpu4;
+ struct ice_hash_gtpu_ctx gtpu6;
+};
+
+struct ice_acl_conf {
+ struct ice_fdir_fltr input;
+ uint64_t input_set;
+};
+
+/**
+ * A structure used to define fields of ACL related info.
+ */
+struct ice_acl_info {
+ struct ice_acl_conf conf;
+ struct rte_bitmap *slots;
+ uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES];
+};
+
struct ice_pf {
struct ice_adapter *adapter; /* The adapter this PF associate to */
struct ice_vsi *main_vsi; /* pointer to main VSI structure */
uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
uint16_t fdir_qp_offset;
struct ice_fdir_info fdir; /* flow director info */
+ struct ice_acl_info acl; /* ACL info */
+ struct ice_hash_ctx hash_ctx;
uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
struct ice_hw_port_stats stats_offset;
bool offset_loaded;
bool adapter_stopped;
struct ice_flow_list flow_list;
+ rte_spinlock_t flow_ops_lock;
struct ice_parser_list rss_parser_list;
struct ice_parser_list perm_parser_list;
struct ice_parser_list dist_parser_list;
+ bool init_link_up;
+ uint64_t old_rx_bytes;
+ uint64_t old_tx_bytes;
+ uint64_t supported_rxdid; /* bitmap for supported RXDID */
+ uint64_t rss_hf;
};
#define ICE_MAX_QUEUE_NUM 2048
+#define ICE_MAX_PIN_NUM 4
/**
* Cache devargs parse result.
*/
struct ice_devargs {
+ int rx_low_latency;
int safe_mode_support;
uint8_t proto_xtr_dflt;
int pipe_mode_support;
uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
+ uint8_t pin_idx;
+ uint8_t pps_out_ena;
};
/**
struct ice_adapter {
/* Common for both PF and VF */
struct ice_hw hw;
- struct rte_eth_dev *eth_dev;
struct ice_pf pf;
bool rx_bulk_alloc_allowed;
bool rx_vec_allowed;
bool is_safe_mode;
struct ice_devargs devargs;
enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
+ uint16_t fdir_ref_cnt;
+ /* For PTP */
+ struct rte_timecounter systime_tc;
+ struct rte_timecounter rx_tstamp_tc;
+ struct rte_timecounter tx_tstamp_tc;
+ bool ptp_ena;
+#ifdef RTE_ARCH_X86
+ bool rx_use_avx2;
+ bool rx_use_avx512;
+ bool tx_use_avx2;
+ bool tx_use_avx512;
+#endif
};
struct ice_vsi_vlan_pvid_info {
(&(((struct ice_vsi *)vsi)->adapter->hw))
#define ICE_VSI_TO_PF(vsi) \
(&(((struct ice_vsi *)vsi)->adapter->pf))
-#define ICE_VSI_TO_ETH_DEV(vsi) \
- (((struct ice_vsi *)vsi)->adapter->eth_dev)
/* ICE_PF_TO */
#define ICE_PF_TO_HW(pf) \
#define ICE_PF_TO_ETH_DEV(pf) \
(((struct ice_pf *)pf)->adapter->eth_dev)
+int
+ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn);
struct ice_vsi *
ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
int
ice_release_vsi(struct ice_vsi *vsi);
+void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
+void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
+void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
+int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
+ struct ice_rss_hash_cfg *cfg);
+int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
+ struct ice_rss_hash_cfg *cfg);
static inline int
ice_align_floor(int n)
git.droids-corp.org / dpdk.git / blobdiff