}
}
+int
+ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
+ struct rte_eth_burst_mode *mode)
+{
+ eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
+ uint64_t options;
+
+ if (pkt_burst == ice_recv_scattered_pkts)
+ options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_SCATTERED;
+ else if (pkt_burst == ice_recv_pkts_bulk_alloc)
+ options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_BULK_ALLOC;
+ else if (pkt_burst == ice_recv_pkts)
+ options = RTE_ETH_BURST_SCALAR;
+#ifdef RTE_ARCH_X86
+ else if (pkt_burst == ice_recv_scattered_pkts_vec_avx2)
+ options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2 |
+ RTE_ETH_BURST_SCATTERED;
+ else if (pkt_burst == ice_recv_pkts_vec_avx2)
+ options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2;
+ else if (pkt_burst == ice_recv_scattered_pkts_vec)
+ options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE |
+ RTE_ETH_BURST_SCATTERED;
+ else if (pkt_burst == ice_recv_pkts_vec)
+ options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE;
+#endif
+ else
+ options = 0;
+
+ mode->options = options;
+
+ return options != 0 ? 0 : -EINVAL;
+}
+
void __attribute__((cold))
ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
{
}
}
+int
+ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
+ struct rte_eth_burst_mode *mode)
+{
+ eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
+ uint64_t options;
+
+ if (pkt_burst == ice_xmit_pkts_simple)
+ options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_SIMPLE;
+ else if (pkt_burst == ice_xmit_pkts)
+ options = RTE_ETH_BURST_SCALAR;
+#ifdef RTE_ARCH_X86
+ else if (pkt_burst == ice_xmit_pkts_vec_avx2)
+ options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2;
+ else if (pkt_burst == ice_xmit_pkts_vec)
+ options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE;
+#endif
+ else
+ options = 0;
+
+ mode->options = options;
+
+ return options != 0 ? 0 : -EINVAL;
+}
+
/* For each value it means, datasheet of hardware can tell more details
*
* @note: fix ice_dev_supported_ptypes_get() if any change here.