ethdev: add speed capabilities

[dpdk.git] / drivers / net / ixgbe / ixgbe_ethdev.c

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 5812d10..894278f 100644 (file)
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -2131,6 +2131,11 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
             !RTE_ETH_DEV_SRIOV(dev).active) &&
            dev->data->dev_conf.intr_conf.rxq != 0) {
                intr_vector = dev->data->nb_rx_queues;
+               if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
+                       PMD_INIT_LOG(ERR, "At most %d intr queues supported",
+                                       IXGBE_MAX_INTR_QUEUE_NUM);
+                       return -ENOTSUP;
+               }
                if (rte_intr_efd_enable(intr_handle, intr_vector))
                        return -1;
        }
@@ -2199,17 +2204,17 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
                                IXGBE_LINK_SPEED_82599_AUTONEG :
                                IXGBE_LINK_SPEED_82598_AUTONEG;
                break;
-       case ETH_LINK_SPEED_100:
+       case ETH_SPEED_NUM_100M:
                /*
                 * Invalid for 82598 but error will be detected by
                 * ixgbe_setup_link()
                 */
                speed = IXGBE_LINK_SPEED_100_FULL;
                break;
-       case ETH_LINK_SPEED_1000:
+       case ETH_SPEED_NUM_1G:
                speed = IXGBE_LINK_SPEED_1GB_FULL;
                break;
-       case ETH_LINK_SPEED_10000:
+       case ETH_SPEED_NUM_10G:
                speed = IXGBE_LINK_SPEED_10GB_FULL;
                break;
        default:
@@ -2960,6 +2965,14 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
        dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
        dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
+
+       dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
+       if (hw->mac.type == ixgbe_mac_X540 ||
+           hw->mac.type == ixgbe_mac_X540_vf ||
+           hw->mac.type == ixgbe_mac_X550 ||
+           hw->mac.type == ixgbe_mac_X550_vf) {
+               dev_info->speed_capa |= ETH_LINK_SPEED_100M;
+       }
 }
 
 static const uint32_t *
@@ -3059,9 +3072,9 @@ ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
        int link_up;
        int diag;
 
-       link.link_status = 0;
+       link.link_status = ETH_LINK_DOWN;
        link.link_speed = 0;
-       link.link_duplex = 0;
+       link.link_duplex = ETH_LINK_HALF_DUPLEX;
        memset(&old, 0, sizeof(old));
        rte_ixgbe_dev_atomic_read_link_status(dev, &old);
 
@@ -3074,7 +3087,7 @@ ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
                diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
 
        if (diag != 0) {
-               link.link_speed = ETH_LINK_SPEED_100;
+               link.link_speed = ETH_SPEED_NUM_100M;
                link.link_duplex = ETH_LINK_HALF_DUPLEX;
                rte_ixgbe_dev_atomic_write_link_status(dev, &link);
                if (link.link_status == old.link_status)
@@ -3088,26 +3101,26 @@ ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
                        return -1;
                return 0;
        }
-       link.link_status = 1;
+       link.link_status = ETH_LINK_UP;
        link.link_duplex = ETH_LINK_FULL_DUPLEX;
 
        switch (link_speed) {
        default:
        case IXGBE_LINK_SPEED_UNKNOWN:
                link.link_duplex = ETH_LINK_HALF_DUPLEX;
-               link.link_speed = ETH_LINK_SPEED_100;
+               link.link_speed = ETH_SPEED_NUM_100M;
                break;
 
        case IXGBE_LINK_SPEED_100_FULL:
-               link.link_speed = ETH_LINK_SPEED_100;
+               link.link_speed = ETH_SPEED_NUM_100M;
                break;
 
        case IXGBE_LINK_SPEED_1GB_FULL:
-               link.link_speed = ETH_LINK_SPEED_1000;
+               link.link_speed = ETH_SPEED_NUM_1G;
                break;
 
        case IXGBE_LINK_SPEED_10GB_FULL:
-               link.link_speed = ETH_LINK_SPEED_10000;
+               link.link_speed = ETH_SPEED_NUM_10G;
                break;
        }
        rte_ixgbe_dev_atomic_write_link_status(dev, &link);
@@ -4442,10 +4455,11 @@ ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
        if (ixgbe_vmdq_mode_check(hw) < 0)
                return -ENOTSUP;
        for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
-               if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
+               if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
                        ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
                        if (ret < 0)
                                return ret;
+               }
        }
 
        return ret;
@@ -5909,15 +5923,15 @@ ixgbe_start_timecounters(struct rte_eth_dev *dev)
        rte_ixgbe_dev_atomic_read_link_status(dev, &link);
 
        switch (link.link_speed) {
-       case ETH_LINK_SPEED_100:
+       case ETH_SPEED_NUM_100M:
                incval = IXGBE_INCVAL_100;
                shift = IXGBE_INCVAL_SHIFT_100;
                break;
-       case ETH_LINK_SPEED_1000:
+       case ETH_SPEED_NUM_1G:
                incval = IXGBE_INCVAL_1GB;
                shift = IXGBE_INCVAL_SHIFT_1GB;
                break;
-       case ETH_LINK_SPEED_10000:
+       case ETH_SPEED_NUM_10G:
        default:
                incval = IXGBE_INCVAL_10GB;
                shift = IXGBE_INCVAL_SHIFT_10GB;