* Copyright(c) 2010-2017 Intel Corporation
*/
-#include <rte_ethdev.h>
+#include <ethdev_driver.h>
#include "base/ixgbe_api.h"
+#include "base/ixgbe_x550.h"
#include "ixgbe_ethdev.h"
#include "rte_pmd_ixgbe.h"
int
rte_pmd_ixgbe_set_vf_mac_addr(uint16_t port, uint16_t vf,
- struct ether_addr *mac_addr)
+ struct rte_ether_addr *mac_addr)
{
struct ixgbe_hw *hw;
struct ixgbe_vf_info *vfinfo;
vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
rar_entry = hw->mac.num_rar_entries - (vf + 1);
- if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
+ if (rte_is_valid_assigned_ether_addr(
+ (struct rte_ether_addr *)new_mac)) {
rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
- ETHER_ADDR_LEN);
+ RTE_ETHER_ADDR_LEN);
return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
IXGBE_RAH_AV);
}
if (vf >= pci_dev->max_vfs)
return -EINVAL;
- if (vlan_id > ETHER_MAX_VLAN_ID)
+ if (vlan_id > RTE_ETHER_MAX_VLAN_ID)
return -EINVAL;
hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
*/
if (hw->mac.type == ixgbe_mac_82598EB)
queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
- ETH_16_POOLS;
+ RTE_ETH_16_POOLS;
else
queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
- ETH_64_POOLS;
+ RTE_ETH_64_POOLS;
for (q = 0; q < queues_per_pool; q++)
(*dev->dev_ops->vlan_strip_queue_set)(dev,
if (!is_ixgbe_supported(dev))
return -ENOTSUP;
- if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
+ if (vlan > RTE_ETHER_MAX_VLAN_ID || vf_mask == 0)
return -EINVAL;
hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
int
rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
{
- struct ixgbe_hw *hw;
struct rte_eth_dev *dev;
- uint32_t ctrl;
+ struct ixgbe_macsec_setting macsec_setting;
RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
if (!is_ixgbe_supported(dev))
return -ENOTSUP;
- hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ macsec_setting.offload_en = 1;
+ macsec_setting.encrypt_en = en;
+ macsec_setting.replayprotect_en = rp;
- /* Stop the data paths */
- if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
- return -ENOTSUP;
- /**
- * Workaround:
- * As no ixgbe_disable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- * The hardware support has been checked by
- * ixgbe_disable_sec_rx_path().
- */
- ixgbe_disable_sec_tx_path_generic(hw);
-
- /* Enable Ethernet CRC (required by MACsec offload) */
- ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
- ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
- IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
-
- /* Enable the TX and RX crypto engines */
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
- ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
- ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
- ctrl |= 0x3;
- IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
-
- /* Enable SA lookup */
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
- ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
- ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
- IXGBE_LSECTXCTRL_AUTH;
- ctrl |= IXGBE_LSECTXCTRL_AISCI;
- ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
- ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
- IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
- ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
- ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
- ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
- if (rp)
- ctrl |= IXGBE_LSECRXCTRL_RP;
- else
- ctrl &= ~IXGBE_LSECRXCTRL_RP;
- IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
-
- /* Start the data paths */
- ixgbe_enable_sec_rx_path(hw);
- /**
- * Workaround:
- * As no ixgbe_enable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- */
- ixgbe_enable_sec_tx_path_generic(hw);
+ ixgbe_dev_macsec_setting_save(dev, &macsec_setting);
+
+ ixgbe_dev_macsec_register_enable(dev, &macsec_setting);
return 0;
}
int
rte_pmd_ixgbe_macsec_disable(uint16_t port)
{
- struct ixgbe_hw *hw;
struct rte_eth_dev *dev;
- uint32_t ctrl;
RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
if (!is_ixgbe_supported(dev))
return -ENOTSUP;
- hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ ixgbe_dev_macsec_setting_reset(dev);
- /* Stop the data paths */
- if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
- return -ENOTSUP;
- /**
- * Workaround:
- * As no ixgbe_disable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- * The hardware support has been checked by
- * ixgbe_disable_sec_rx_path().
- */
- ixgbe_disable_sec_tx_path_generic(hw);
-
- /* Disable the TX and RX crypto engines */
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
- ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
- ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
- IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
-
- /* Disable SA lookup */
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
- ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
- ctrl |= IXGBE_LSECTXCTRL_DISABLE;
- IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
-
- ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
- ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
- ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
- IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
-
- /* Start the data paths */
- ixgbe_enable_sec_rx_path(hw);
- /**
- * Workaround:
- * As no ixgbe_enable_sec_rx_path equivalent is
- * implemented for tx in the base code, and we are
- * not allowed to modify the base code in DPDK, so
- * just call the hand-written one directly for now.
- */
- ixgbe_enable_sec_tx_path_generic(hw);
+ ixgbe_dev_macsec_register_disable(dev);
return 0;
}
bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
eth_conf = &dev->data->dev_conf;
- if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
+ if (eth_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) {
nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
- } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
+ } else if (eth_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) {
if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
- ETH_32_POOLS)
- nb_tcs = ETH_4_TCS;
+ RTE_ETH_32_POOLS)
+ nb_tcs = RTE_ETH_4_TCS;
else
- nb_tcs = ETH_8_TCS;
+ nb_tcs = RTE_ETH_8_TCS;
} else {
nb_tcs = 1;
}
return 0;
}
+int
+rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable)
+{
+ struct ixgbe_hw *hw;
+ struct rte_eth_dev *dev;
+ uint32_t fctrl;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ if (!hw)
+ return -ENOTSUP;
+
+ fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+
+ /* If 'enable' set the SBP bit else clear it */
+ if (enable)
+ fctrl |= IXGBE_FCTRL_SBP;
+ else
+ fctrl &= ~(IXGBE_FCTRL_SBP);
+
+ IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
+ return 0;
+}
+
#ifdef RTE_LIBRTE_IXGBE_BYPASS
int
rte_pmd_ixgbe_bypass_init(uint16_t port_id)
return ixgbe_bypass_wd_reset(dev);
}
#endif
+
+/**
+ * rte_pmd_ixgbe_acquire_swfw - Acquire SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to acquire
+ *
+ * Acquires the SWFW semaphore and get the shared phy token as needed
+ */
+STATIC s32 rte_pmd_ixgbe_acquire_swfw(struct ixgbe_hw *hw, u32 mask)
+{
+ int retries = FW_PHY_TOKEN_RETRIES;
+ s32 status = IXGBE_SUCCESS;
+
+ while (--retries) {
+ status = ixgbe_acquire_swfw_semaphore(hw, mask);
+ if (status) {
+ PMD_DRV_LOG(ERR, "Get SWFW sem failed, Status = %d\n",
+ status);
+ return status;
+ }
+ status = ixgbe_get_phy_token(hw);
+ if (status == IXGBE_SUCCESS)
+ return IXGBE_SUCCESS;
+
+ if (status == IXGBE_ERR_TOKEN_RETRY)
+ PMD_DRV_LOG(ERR, "Get PHY token failed, Status = %d\n",
+ status);
+
+ ixgbe_release_swfw_semaphore(hw, mask);
+ if (status != IXGBE_ERR_TOKEN_RETRY) {
+ PMD_DRV_LOG(ERR,
+ "Retry get PHY token failed, Status=%d\n",
+ status);
+ return status;
+ }
+ }
+ PMD_DRV_LOG(ERR, "swfw acquisition retries failed!: PHY ID = 0x%08X\n",
+ hw->phy.id);
+ return status;
+}
+
+/**
+ * rte_pmd_ixgbe_release_swfw_sync - Release SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to release
+ *
+ * Releases the SWFW semaphore and puts the shared phy token as needed
+ */
+STATIC void rte_pmd_ixgbe_release_swfw(struct ixgbe_hw *hw, u32 mask)
+{
+ ixgbe_put_phy_token(hw);
+ ixgbe_release_swfw_semaphore(hw, mask);
+}
+
+int
+rte_pmd_ixgbe_mdio_lock(uint16_t port)
+{
+ struct ixgbe_hw *hw;
+ struct rte_eth_dev *dev;
+ u32 swfw_mask;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ if (!hw)
+ return -ENOTSUP;
+
+ if (hw->bus.lan_id)
+ swfw_mask = IXGBE_GSSR_PHY1_SM;
+ else
+ swfw_mask = IXGBE_GSSR_PHY0_SM;
+
+ if (rte_pmd_ixgbe_acquire_swfw(hw, swfw_mask))
+ return IXGBE_ERR_SWFW_SYNC;
+
+ return IXGBE_SUCCESS;
+}
+
+int
+rte_pmd_ixgbe_mdio_unlock(uint16_t port)
+{
+ struct rte_eth_dev *dev;
+ struct ixgbe_hw *hw;
+ u32 swfw_mask;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ if (!hw)
+ return -ENOTSUP;
+
+ if (hw->bus.lan_id)
+ swfw_mask = IXGBE_GSSR_PHY1_SM;
+ else
+ swfw_mask = IXGBE_GSSR_PHY0_SM;
+
+ rte_pmd_ixgbe_release_swfw(hw, swfw_mask);
+
+ return IXGBE_SUCCESS;
+}
+
+int
+rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
+ uint32_t dev_type, uint16_t *phy_data)
+{
+ struct ixgbe_hw *hw;
+ struct rte_eth_dev *dev;
+ u32 i, data, command;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ if (!hw)
+ return -ENOTSUP;
+
+ /* Setup and write the read command */
+ command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+ (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+ IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
+ IXGBE_MSCA_MDI_COMMAND;
+
+ IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+ /* Check every 10 usec to see if the access completed.
+ * The MDI Command bit will clear when the operation is
+ * complete
+ */
+ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+ usec_delay(10);
+
+ command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+ if (!(command & IXGBE_MSCA_MDI_COMMAND))
+ break;
+ }
+ if (command & IXGBE_MSCA_MDI_COMMAND)
+ return IXGBE_ERR_PHY;
+
+ /* Read operation is complete. Get the data from MSRWD */
+ data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
+ data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
+ *phy_data = (u16)data;
+
+ return 0;
+}
+
+int
+rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr,
+ uint32_t dev_type, uint16_t phy_data)
+{
+ struct ixgbe_hw *hw;
+ u32 i, command;
+ struct rte_eth_dev *dev;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ if (!hw)
+ return -ENOTSUP;
+
+ /* Put the data in the MDI single read and write data register*/
+ IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
+
+ /* Setup and write the write command */
+ command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+ (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+ IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
+ IXGBE_MSCA_MDI_COMMAND;
+
+ IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+ /* Check every 10 usec to see if the access completed.
+ * The MDI Command bit will clear when the operation is
+ * complete
+ */
+ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+ usec_delay(10);
+
+ command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+ if (!(command & IXGBE_MSCA_MDI_COMMAND))
+ break;
+ }
+ if (command & IXGBE_MSCA_MDI_COMMAND) {
+ ERROR_REPORT1(IXGBE_ERROR_POLLING,
+ "PHY write cmd didn't complete\n");
+ return IXGBE_ERR_PHY;
+ }
+ return 0;
+}
+
+int
+rte_pmd_ixgbe_get_fdir_info(uint16_t port, struct rte_eth_fdir_info *fdir_info)
+{
+ struct rte_eth_dev *dev;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ ixgbe_fdir_info_get(dev, fdir_info);
+
+ return 0;
+}
+
+int
+rte_pmd_ixgbe_get_fdir_stats(uint16_t port,
+ struct rte_eth_fdir_stats *fdir_stats)
+{
+ struct rte_eth_dev *dev;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
+
+ dev = &rte_eth_devices[port];
+ if (!is_ixgbe_supported(dev))
+ return -ENOTSUP;
+
+ ixgbe_fdir_stats_get(dev, fdir_stats);
+
+ return 0;
+}
git.droids-corp.org / dpdk.git / blobdiff