net/mlx5: convert Rx timestamps in real-time format

[dpdk.git] / drivers / net / mlx5 / linux / mlx5_os.c

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 2dc57b2..f228bab 100644 (file)
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -630,12 +630,6 @@ err_secondary:
        priv->mtu = RTE_ETHER_MTU;
        priv->mp_id.port_id = port_id;
        strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
-#ifndef RTE_ARCH_64
-       /* Initialize UAR access locks for 32bit implementations. */
-       rte_spinlock_init(&priv->uar_lock_cq);
-       for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
-               rte_spinlock_init(&priv->uar_lock[i]);
-#endif
        /* Some internal functions rely on Netlink sockets, open them now. */
        priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
        priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
@@ -879,6 +873,90 @@ err_secondary:
                }
 #endif
        }
+       if (config.tx_pp) {
+               DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz",
+                       config.hca_attr.dev_freq_khz);
+               DRV_LOG(DEBUG, "Packet pacing is %ssupported",
+                       config.hca_attr.qos.packet_pacing ? "" : "not ");
+               DRV_LOG(DEBUG, "Cross channel ops are %ssupported",
+                       config.hca_attr.cross_channel ? "" : "not ");
+               DRV_LOG(DEBUG, "WQE index ignore is %ssupported",
+                       config.hca_attr.wqe_index_ignore ? "" : "not ");
+               DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported",
+                       config.hca_attr.non_wire_sq ? "" : "not ");
+               DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)",
+                       config.hca_attr.log_max_static_sq_wq ? "" : "not ",
+                       config.hca_attr.log_max_static_sq_wq);
+               DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported",
+                       config.hca_attr.qos.wqe_rate_pp ? "" : "not ");
+               if (!config.devx) {
+                       DRV_LOG(ERR, "DevX is required for packet pacing");
+                       err = ENODEV;
+                       goto error;
+               }
+               if (!config.hca_attr.qos.packet_pacing) {
+                       DRV_LOG(ERR, "Packet pacing is not supported");
+                       err = ENODEV;
+                       goto error;
+               }
+               if (!config.hca_attr.cross_channel) {
+                       DRV_LOG(ERR, "Cross channel operations are"
+                                    " required for packet pacing");
+                       err = ENODEV;
+                       goto error;
+               }
+               if (!config.hca_attr.wqe_index_ignore) {
+                       DRV_LOG(ERR, "WQE index ignore feature is"
+                                    " required for packet pacing");
+                       err = ENODEV;
+                       goto error;
+               }
+               if (!config.hca_attr.non_wire_sq) {
+                       DRV_LOG(ERR, "Non-wire SQ feature is"
+                                    " required for packet pacing");
+                       err = ENODEV;
+                       goto error;
+               }
+               if (!config.hca_attr.log_max_static_sq_wq) {
+                       DRV_LOG(ERR, "Static WQE SQ feature is"
+                                    " required for packet pacing");
+                       err = ENODEV;
+                       goto error;
+               }
+               if (!config.hca_attr.qos.wqe_rate_pp) {
+                       DRV_LOG(ERR, "WQE rate mode is required"
+                                    " for packet pacing");
+                       err = ENODEV;
+                       goto error;
+               }
+#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
+               DRV_LOG(ERR, "DevX does not provide UAR offset,"
+                            " can't create queues for packet pacing");
+               err = ENODEV;
+               goto error;
+#endif
+       }
+       if (config.devx) {
+               uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
+
+               err = mlx5_devx_cmd_register_read
+                       (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
+                       reg, MLX5_ST_SZ_DW(register_mtutc));
+               if (!err) {
+                       uint32_t ts_mode;
+
+                       /* MTUTC register is read successfully. */
+                       ts_mode = MLX5_GET(register_mtutc, reg,
+                                          time_stamp_mode);
+                       if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
+                               config.rt_timestamp = 1;
+               } else {
+                       /* Kernel does not support register reading. */
+                       if (config.hca_attr.dev_freq_khz ==
+                                                (NS_PER_S / MS_PER_S))
+                               config.rt_timestamp = 1;
+               }
+       }
        if (config.mprq.enabled && mprq) {
                if (config.mprq.stride_num_n &&
                    (config.mprq.stride_num_n > mprq_max_stride_num_n ||
@@ -1812,6 +1890,9 @@ mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
 {
        int dbmap_env;
        int err = 0;
+
+       sh->numa_node = spawn->pci_dev->device.numa_node;
+       pthread_mutex_init(&sh->txpp.mutex, NULL);
        /*
         * Configure environment variable "MLX5_BF_SHUT_UP"
         * before the device creation. The rdma_core library
@@ -2288,7 +2369,7 @@ const struct eth_dev_ops mlx5_os_dev_ops = {
        .xstats_get_names = mlx5_xstats_get_names,
        .fw_version_get = mlx5_fw_version_get,
        .dev_infos_get = mlx5_dev_infos_get,
-       .read_clock = mlx5_read_clock,
+       .read_clock = mlx5_txpp_read_clock,
        .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
        .vlan_filter_set = mlx5_vlan_filter_set,
        .rx_queue_setup = mlx5_rx_queue_setup,
@@ -2337,6 +2418,7 @@ const struct eth_dev_ops mlx5_os_dev_sec_ops = {
        .xstats_get_names = mlx5_xstats_get_names,
        .fw_version_get = mlx5_fw_version_get,
        .dev_infos_get = mlx5_dev_infos_get,
+       .read_clock = mlx5_txpp_read_clock,
        .rx_descriptor_status = mlx5_rx_descriptor_status,
        .tx_descriptor_status = mlx5_tx_descriptor_status,
        .rxq_info_get = mlx5_rxq_info_get,
@@ -2367,6 +2449,7 @@ const struct eth_dev_ops mlx5_os_dev_ops_isolate = {
        .xstats_get_names = mlx5_xstats_get_names,
        .fw_version_get = mlx5_fw_version_get,
        .dev_infos_get = mlx5_dev_infos_get,
+       .read_clock = mlx5_txpp_read_clock,
        .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
        .vlan_filter_set = mlx5_vlan_filter_set,
        .rx_queue_setup = mlx5_rx_queue_setup,