#include <errno.h>
#include <rte_malloc.h>
-#include <rte_ethdev_driver.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_driver.h>
+#include <ethdev_pci.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_common.h>
#include <rte_spinlock.h>
#include <rte_string_fns.h>
#include <rte_alarm.h>
+#include <rte_cycles.h>
#include <mlx5_glue.h>
#include <mlx5_devx_cmds.h>
#include "mlx5.h"
#include "mlx5_utils.h"
#include "mlx5_rxtx.h"
+#include "mlx5_rx.h"
+#include "mlx5_tx.h"
#include "mlx5_autoconf.h"
#include "mlx5_mr.h"
#include "mlx5_flow.h"
+#include "mlx5_flow_os.h"
#include "rte_pmd_mlx5.h"
/* Device parameter to enable RX completion queue compression. */
#define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
-/* Device parameter to enable RX completion entry padding to 128B. */
-#define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
-
/* Device parameter to enable padding Rx packet to cacheline size. */
#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
LIST_HEAD_INITIALIZER();
-static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
-
+static pthread_mutex_t mlx5_dev_ctx_list_mutex;
static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- {
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+ [MLX5_IPOOL_DECAP_ENCAP] = {
.size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_encap_decap_ipool",
},
- {
+ [MLX5_IPOOL_PUSH_VLAN] = {
.size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_push_vlan_ipool",
},
- {
+ [MLX5_IPOOL_TAG] = {
.size = sizeof(struct mlx5_flow_dv_tag_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_tag_ipool",
},
- {
+ [MLX5_IPOOL_PORT_ID] = {
.size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_port_id_ipool",
},
- {
+ [MLX5_IPOOL_JUMP] = {
.size = sizeof(struct mlx5_flow_tbl_data_entry),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_jump_ipool",
},
- {
+ [MLX5_IPOOL_SAMPLE] = {
.size = sizeof(struct mlx5_flow_dv_sample_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_sample_ipool",
},
- {
+ [MLX5_IPOOL_DEST_ARRAY] = {
.size = sizeof(struct mlx5_flow_dv_dest_array_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_dest_array_ipool",
},
+ [MLX5_IPOOL_TUNNEL_ID] = {
+ .size = sizeof(struct mlx5_flow_tunnel),
+ .trunk_size = MLX5_MAX_TUNNELS,
+ .need_lock = 1,
+ .release_mem_en = 1,
+ .type = "mlx5_tunnel_offload",
+ },
+ [MLX5_IPOOL_TNL_TBL_ID] = {
+ .size = 0,
+ .need_lock = 1,
+ .type = "mlx5_flow_tnl_tbl_ipool",
+ },
#endif
- {
+ [MLX5_IPOOL_MTR] = {
.size = sizeof(struct mlx5_flow_meter),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_meter_ipool",
},
- {
+ [MLX5_IPOOL_MCP] = {
.size = sizeof(struct mlx5_flow_mreg_copy_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_mcp_ipool",
},
- {
+ [MLX5_IPOOL_HRXQ] = {
.size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_hrxq_ipool",
},
- {
+ [MLX5_IPOOL_MLX5_FLOW] = {
/*
* MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
* It set in run time according to PCI function configuration.
.free = mlx5_free,
.type = "mlx5_flow_handle_ipool",
},
- {
+ [MLX5_IPOOL_RTE_FLOW] = {
.size = sizeof(struct rte_flow),
.trunk_size = 4096,
.need_lock = 1,
.free = mlx5_free,
.type = "rte_flow_ipool",
},
- {
+ [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
.size = 0,
.need_lock = 1,
.type = "mlx5_flow_rss_id_ipool",
},
- {
- .size = 0,
- .need_lock = 1,
- .type = "mlx5_flow_tnl_flow_ipool",
- },
- {
- .size = 0,
+ [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
+ .size = sizeof(struct mlx5_shared_action_rss),
+ .trunk_size = 64,
+ .grow_trunk = 3,
+ .grow_shift = 2,
.need_lock = 1,
- .type = "mlx5_flow_tnl_tbl_ipool",
+ .release_mem_en = 1,
+ .malloc = mlx5_malloc,
+ .free = mlx5_free,
+ .type = "mlx5_shared_action_rss",
},
};
#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
+/**
+ * Decide whether representor ID is a HPF(host PF) port on BF2.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ *
+ * @return
+ * Non-zero if HPF, otherwise 0.
+ */
+bool
+mlx5_is_hpf(struct rte_eth_dev *dev)
+{
+ struct mlx5_priv *priv = dev->data->dev_private;
+ uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
+ int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
+
+ return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
+ MLX5_REPRESENTOR_REPR(-1) == repr;
+}
+
+/**
+ * Initialize the ASO aging management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
+{
+ int err;
+
+ if (sh->aso_age_mng)
+ return 0;
+ sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
+ RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
+ if (!sh->aso_age_mng) {
+ DRV_LOG(ERR, "aso_age_mng allocation was failed.");
+ rte_errno = ENOMEM;
+ return -ENOMEM;
+ }
+ err = mlx5_aso_queue_init(sh);
+ if (err) {
+ mlx5_free(sh->aso_age_mng);
+ return -1;
+ }
+ rte_spinlock_init(&sh->aso_age_mng->resize_sl);
+ rte_spinlock_init(&sh->aso_age_mng->free_sl);
+ LIST_INIT(&sh->aso_age_mng->free);
+ return 0;
+}
+
+/**
+ * Close and release all the resources of the ASO aging management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free.
+ */
+static void
+mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
+{
+ int i, j;
+
+ mlx5_aso_queue_stop(sh);
+ mlx5_aso_queue_uninit(sh);
+ if (sh->aso_age_mng->pools) {
+ struct mlx5_aso_age_pool *pool;
+
+ for (i = 0; i < sh->aso_age_mng->next; ++i) {
+ pool = sh->aso_age_mng->pools[i];
+ claim_zero(mlx5_devx_cmd_destroy
+ (pool->flow_hit_aso_obj));
+ for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
+ if (pool->actions[j].dr_action)
+ claim_zero
+ (mlx5_flow_os_destroy_flow_action
+ (pool->actions[j].dr_action));
+ mlx5_free(pool);
+ }
+ mlx5_free(sh->aso_age_mng->pools);
+ }
+ mlx5_free(sh->aso_age_mng);
+}
+
/**
* Initialize the shared aging list information per port.
*
age_info = &sh->port[i].age_info;
age_info->flags = 0;
TAILQ_INIT(&age_info->aged_counters);
+ LIST_INIT(&age_info->aged_aso);
rte_spinlock_init(&age_info->aged_sl);
MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
}
LIST_REMOVE(mng, next);
claim_zero(mlx5_devx_cmd_destroy(mng->dm));
- claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
+ claim_zero(mlx5_os_umem_dereg(mng->umem));
mlx5_free(mem);
}
if (cnt->action)
claim_zero
- (mlx5_glue->destroy_flow_action
+ (mlx5_flow_os_destroy_flow_action
(cnt->action));
if (fallback && MLX5_POOL_GET_CNT
(pool, j)->dcs_when_free)
memset(&sh->cmng, 0, sizeof(sh->cmng));
}
+/* Send FLOW_AGED event if needed. */
+void
+mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
+{
+ struct mlx5_age_info *age_info;
+ uint32_t i;
+
+ for (i = 0; i < sh->max_port; i++) {
+ age_info = &sh->port[i].age_info;
+ if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
+ continue;
+ if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
+ rte_eth_dev_callback_process
+ (&rte_eth_devices[sh->port[i].devx_ih_port_id],
+ RTE_ETH_EVENT_FLOW_AGED, NULL);
+ age_info->flags = 0;
+ }
+}
+
/**
* Initialize the flow resources' indexed mempool.
*
* the UAR mapping type into account on UAR setup
* on queue creation.
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->tx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* If Verbs/kernel does not support "Non-Cached"
* try the "Write-Combining".
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
sh->tx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
sh->tx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
* should be no datapath noticeable impact,
* can try "Non-Cached" mapping safely.
*/
- DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
sh->devx_rx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
rte_errno = ENOMEM;
goto exit;
}
+ if (spawn->bond_info)
+ sh->bond = *spawn->bond_info;
err = mlx5_os_open_device(spawn, config, sh);
if (!sh->ctx)
goto error;
sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
}
- sh->pd = mlx5_glue->alloc_pd(sh->ctx);
+ sh->pd = mlx5_os_alloc_pd(sh->ctx);
if (sh->pd == NULL) {
DRV_LOG(ERR, "PD allocation failure");
err = ENOMEM;
goto error;
}
if (sh->devx) {
- /* Query the EQN for this core. */
- err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
- if (err) {
- rte_errno = errno;
- DRV_LOG(ERR, "Failed to query event queue number %d.",
- rte_errno);
- goto error;
- }
err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
if (err) {
DRV_LOG(ERR, "Fail to extract pdn from PD");
err = rte_errno;
goto error;
}
+ if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
+ err = mlx5_flow_os_init_workspace_once();
+ if (err)
+ goto error;
+ }
mlx5_flow_aging_init(sh);
mlx5_flow_counters_mng_init(sh);
mlx5_flow_ipool_create(sh, config);
rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
/* Add context to the global device list. */
LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
+ rte_spinlock_init(&sh->geneve_tlv_opt_sl);
exit:
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
return sh;
if (sh->tx_uar)
mlx5_glue->devx_free_uar(sh->tx_uar);
if (sh->pd)
- claim_zero(mlx5_glue->dealloc_pd(sh->pd));
+ claim_zero(mlx5_os_dealloc_pd(sh->pd));
if (sh->ctx)
claim_zero(mlx5_glue->close_device(sh->ctx));
mlx5_free(sh);
mlx5_mr_release_cache(&sh->share_cache);
/* Remove context from the global device list. */
LIST_REMOVE(sh, next);
+ /* Release flow workspaces objects on the last device. */
+ if (LIST_EMPTY(&mlx5_dev_ctx_list))
+ mlx5_flow_os_release_workspace();
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
/*
* Ensure there is no async event handler installed.
* Only primary process handles async device events.
**/
mlx5_flow_counters_mng_close(sh);
+ if (sh->aso_age_mng) {
+ mlx5_flow_aso_age_mng_close(sh);
+ sh->aso_age_mng = NULL;
+ }
mlx5_flow_ipool_destroy(sh);
mlx5_os_dev_shared_handler_uninstall(sh);
if (sh->cnt_id_tbl) {
sh->tx_uar = NULL;
}
if (sh->pd)
- claim_zero(mlx5_glue->dealloc_pd(sh->pd));
+ claim_zero(mlx5_os_dealloc_pd(sh->pd));
if (sh->tis)
claim_zero(mlx5_devx_cmd_destroy(sh->tis));
if (sh->td)
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
if (sh->ctx)
claim_zero(mlx5_glue->close_device(sh->ctx));
+ MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
pthread_mutex_destroy(&sh->txpp.mutex);
mlx5_free(sh);
return;
{
int err = 0;
/* Tables are only used in DV and DR modes. */
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
struct mlx5_dev_ctx_shared *sh = priv->sh;
char s[MLX5_HLIST_NAMESIZE];
MLX5_ASSERT(sh);
snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
- 0, 0, flow_dv_tbl_create_cb, NULL,
+ 0, 0, flow_dv_tbl_create_cb,
+ flow_dv_tbl_match_cb,
flow_dv_tbl_remove_cb);
if (!sh->flow_tbls) {
DRV_LOG(ERR, "flow tables with hash creation failed.");
*/
ppriv_size =
sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
- ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
- dev->device->numa_node);
+ ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
+ RTE_CACHE_LINE_SIZE, dev->device->numa_node);
if (!ppriv) {
rte_errno = ENOMEM;
return -rte_errno;
}
- ppriv->uar_table_sz = ppriv_size;
+ ppriv->uar_table_sz = priv->txqs_n;
dev->process_private = ppriv;
return 0;
}
* @param dev
* Pointer to Ethernet device structure.
*/
-static void
+void
mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
{
if (!dev->process_private)
* then this will return directly without any action.
*/
mlx5_flow_list_flush(dev, &priv->flows, true);
- mlx5_shared_action_flush(dev);
+ mlx5_action_handle_flush(dev);
mlx5_flow_meter_flush(dev, NULL);
/* Prevent crashes when queues are still in use. */
dev->rx_pkt_burst = removed_rx_burst;
mlx5_flex_parser_ecpri_release(dev);
if (priv->rxqs != NULL) {
/* XXX race condition if mlx5_rx_burst() is still running. */
- usleep(1000);
+ rte_delay_us_sleep(1000);
for (i = 0; (i != priv->rxqs_n); ++i)
mlx5_rxq_release(dev, i);
priv->rxqs_n = 0;
}
if (priv->txqs != NULL) {
/* XXX race condition if mlx5_tx_burst() is still running. */
- usleep(1000);
+ rte_delay_us_sleep(1000);
for (i = 0; (i != priv->txqs_n); ++i)
mlx5_txq_release(dev, i);
priv->txqs_n = 0;
priv->txqs = NULL;
}
mlx5_proc_priv_uninit(dev);
+ if (priv->q_counters) {
+ mlx5_devx_cmd_destroy(priv->q_counters);
+ priv->q_counters = NULL;
+ }
if (priv->drop_queue.hrxq)
mlx5_drop_action_destroy(dev);
if (priv->mreg_cp_tbl)
if (ret)
DRV_LOG(WARNING, "port %u some flows still remain",
dev->data->port_id);
+ mlx5_cache_list_destroy(&priv->hrxqs);
/*
* Free the shared context in last turn, because the cleanup
* routines above may use some shared fields, like
return 0;
}
+const struct eth_dev_ops mlx5_dev_ops = {
+ .dev_configure = mlx5_dev_configure,
+ .dev_start = mlx5_dev_start,
+ .dev_stop = mlx5_dev_stop,
+ .dev_set_link_down = mlx5_set_link_down,
+ .dev_set_link_up = mlx5_set_link_up,
+ .dev_close = mlx5_dev_close,
+ .promiscuous_enable = mlx5_promiscuous_enable,
+ .promiscuous_disable = mlx5_promiscuous_disable,
+ .allmulticast_enable = mlx5_allmulticast_enable,
+ .allmulticast_disable = mlx5_allmulticast_disable,
+ .link_update = mlx5_link_update,
+ .stats_get = mlx5_stats_get,
+ .stats_reset = mlx5_stats_reset,
+ .xstats_get = mlx5_xstats_get,
+ .xstats_reset = mlx5_xstats_reset,
+ .xstats_get_names = mlx5_xstats_get_names,
+ .fw_version_get = mlx5_fw_version_get,
+ .dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
+ .read_clock = mlx5_txpp_read_clock,
+ .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
+ .vlan_filter_set = mlx5_vlan_filter_set,
+ .rx_queue_setup = mlx5_rx_queue_setup,
+ .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
+ .tx_queue_setup = mlx5_tx_queue_setup,
+ .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
+ .rx_queue_release = mlx5_rx_queue_release,
+ .tx_queue_release = mlx5_tx_queue_release,
+ .rx_queue_start = mlx5_rx_queue_start,
+ .rx_queue_stop = mlx5_rx_queue_stop,
+ .tx_queue_start = mlx5_tx_queue_start,
+ .tx_queue_stop = mlx5_tx_queue_stop,
+ .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
+ .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
+ .mac_addr_remove = mlx5_mac_addr_remove,
+ .mac_addr_add = mlx5_mac_addr_add,
+ .mac_addr_set = mlx5_mac_addr_set,
+ .set_mc_addr_list = mlx5_set_mc_addr_list,
+ .mtu_set = mlx5_dev_set_mtu,
+ .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
+ .vlan_offload_set = mlx5_vlan_offload_set,
+ .reta_update = mlx5_dev_rss_reta_update,
+ .reta_query = mlx5_dev_rss_reta_query,
+ .rss_hash_update = mlx5_rss_hash_update,
+ .rss_hash_conf_get = mlx5_rss_hash_conf_get,
+ .flow_ops_get = mlx5_flow_ops_get,
+ .rxq_info_get = mlx5_rxq_info_get,
+ .txq_info_get = mlx5_txq_info_get,
+ .rx_burst_mode_get = mlx5_rx_burst_mode_get,
+ .tx_burst_mode_get = mlx5_tx_burst_mode_get,
+ .rx_queue_intr_enable = mlx5_rx_intr_enable,
+ .rx_queue_intr_disable = mlx5_rx_intr_disable,
+ .is_removed = mlx5_is_removed,
+ .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
+ .get_module_info = mlx5_get_module_info,
+ .get_module_eeprom = mlx5_get_module_eeprom,
+ .hairpin_cap_get = mlx5_hairpin_cap_get,
+ .mtr_ops_get = mlx5_flow_meter_ops_get,
+ .hairpin_bind = mlx5_hairpin_bind,
+ .hairpin_unbind = mlx5_hairpin_unbind,
+ .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
+ .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
+ .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
+ .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+};
+
+/* Available operations from secondary process. */
+const struct eth_dev_ops mlx5_dev_sec_ops = {
+ .stats_get = mlx5_stats_get,
+ .stats_reset = mlx5_stats_reset,
+ .xstats_get = mlx5_xstats_get,
+ .xstats_reset = mlx5_xstats_reset,
+ .xstats_get_names = mlx5_xstats_get_names,
+ .fw_version_get = mlx5_fw_version_get,
+ .dev_infos_get = mlx5_dev_infos_get,
+ .read_clock = mlx5_txpp_read_clock,
+ .rx_queue_start = mlx5_rx_queue_start,
+ .rx_queue_stop = mlx5_rx_queue_stop,
+ .tx_queue_start = mlx5_tx_queue_start,
+ .tx_queue_stop = mlx5_tx_queue_stop,
+ .rxq_info_get = mlx5_rxq_info_get,
+ .txq_info_get = mlx5_txq_info_get,
+ .rx_burst_mode_get = mlx5_rx_burst_mode_get,
+ .tx_burst_mode_get = mlx5_tx_burst_mode_get,
+ .get_module_info = mlx5_get_module_info,
+ .get_module_eeprom = mlx5_get_module_eeprom,
+};
+
+/* Available operations in flow isolated mode. */
+const struct eth_dev_ops mlx5_dev_ops_isolate = {
+ .dev_configure = mlx5_dev_configure,
+ .dev_start = mlx5_dev_start,
+ .dev_stop = mlx5_dev_stop,
+ .dev_set_link_down = mlx5_set_link_down,
+ .dev_set_link_up = mlx5_set_link_up,
+ .dev_close = mlx5_dev_close,
+ .promiscuous_enable = mlx5_promiscuous_enable,
+ .promiscuous_disable = mlx5_promiscuous_disable,
+ .allmulticast_enable = mlx5_allmulticast_enable,
+ .allmulticast_disable = mlx5_allmulticast_disable,
+ .link_update = mlx5_link_update,
+ .stats_get = mlx5_stats_get,
+ .stats_reset = mlx5_stats_reset,
+ .xstats_get = mlx5_xstats_get,
+ .xstats_reset = mlx5_xstats_reset,
+ .xstats_get_names = mlx5_xstats_get_names,
+ .fw_version_get = mlx5_fw_version_get,
+ .dev_infos_get = mlx5_dev_infos_get,
+ .read_clock = mlx5_txpp_read_clock,
+ .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
+ .vlan_filter_set = mlx5_vlan_filter_set,
+ .rx_queue_setup = mlx5_rx_queue_setup,
+ .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
+ .tx_queue_setup = mlx5_tx_queue_setup,
+ .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
+ .rx_queue_release = mlx5_rx_queue_release,
+ .tx_queue_release = mlx5_tx_queue_release,
+ .rx_queue_start = mlx5_rx_queue_start,
+ .rx_queue_stop = mlx5_rx_queue_stop,
+ .tx_queue_start = mlx5_tx_queue_start,
+ .tx_queue_stop = mlx5_tx_queue_stop,
+ .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
+ .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
+ .mac_addr_remove = mlx5_mac_addr_remove,
+ .mac_addr_add = mlx5_mac_addr_add,
+ .mac_addr_set = mlx5_mac_addr_set,
+ .set_mc_addr_list = mlx5_set_mc_addr_list,
+ .mtu_set = mlx5_dev_set_mtu,
+ .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
+ .vlan_offload_set = mlx5_vlan_offload_set,
+ .flow_ops_get = mlx5_flow_ops_get,
+ .rxq_info_get = mlx5_rxq_info_get,
+ .txq_info_get = mlx5_txq_info_get,
+ .rx_burst_mode_get = mlx5_rx_burst_mode_get,
+ .tx_burst_mode_get = mlx5_tx_burst_mode_get,
+ .rx_queue_intr_enable = mlx5_rx_intr_enable,
+ .rx_queue_intr_disable = mlx5_rx_intr_disable,
+ .is_removed = mlx5_is_removed,
+ .get_module_info = mlx5_get_module_info,
+ .get_module_eeprom = mlx5_get_module_eeprom,
+ .hairpin_cap_get = mlx5_hairpin_cap_get,
+ .mtr_ops_get = mlx5_flow_meter_ops_get,
+ .hairpin_bind = mlx5_hairpin_bind,
+ .hairpin_unbind = mlx5_hairpin_unbind,
+ .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
+ .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
+ .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
+ .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+};
+
/**
* Verify and store value for device argument.
*
}
mod = tmp >= 0 ? tmp : -tmp;
if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
+ if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
+ DRV_LOG(ERR, "invalid CQE compression "
+ "format parameter");
+ rte_errno = EINVAL;
+ return -rte_errno;
+ }
config->cqe_comp = !!tmp;
- } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
- config->cqe_pad = !!tmp;
+ config->cqe_comp_fmt = tmp;
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
{
const char **params = (const char *[]){
MLX5_RXQ_CQE_COMP_EN,
- MLX5_RXQ_CQE_PAD_EN,
MLX5_RXQ_PKT_PAD_EN,
MLX5_RX_MPRQ_EN,
MLX5_RX_MPRQ_LOG_STRIDE_NUM,
(dev->device == &pci_dev->device ||
(dev->device->driver &&
dev->device->driver->name &&
- !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
+ !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
break;
port_id++;
}
},
{
RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
- PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
+ PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
},
{
RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
.driver_class = MLX5_CLASS_NET,
.pci_driver = {
.driver = {
- .name = MLX5_DRIVER_NAME,
+ .name = MLX5_PCI_DRIVER_NAME,
},
.id_table = mlx5_pci_id_map,
.probe = mlx5_os_pci_probe,
*/
RTE_INIT(rte_mlx5_pmd_init)
{
+ pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
mlx5_common_init();
/* Build the static tables for Verbs conversion. */
mlx5_set_ptype_table();
git.droids-corp.org / dpdk.git / blobdiff