#include <errno.h>
#include <rte_malloc.h>
-#include <rte_ethdev_driver.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_driver.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_common.h>
#include <mlx5_common.h>
#include <mlx5_common_os.h>
#include <mlx5_common_mp.h>
-#include <mlx5_common_pci.h>
#include <mlx5_malloc.h>
#include "mlx5_defs.h"
#include "mlx5.h"
#include "mlx5_utils.h"
#include "mlx5_rxtx.h"
+#include "mlx5_rx.h"
+#include "mlx5_tx.h"
#include "mlx5_autoconf.h"
#include "mlx5_mr.h"
#include "mlx5_flow.h"
#include "mlx5_flow_os.h"
#include "rte_pmd_mlx5.h"
+#define MLX5_ETH_DRIVER_NAME mlx5_eth
+
/* Device parameter to enable RX completion queue compression. */
#define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
-/* Device parameter to enable RX completion entry padding to 128B. */
-#define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
-
/* Device parameter to enable padding Rx packet to cacheline size. */
#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
/* Decap will be used or not. */
#define MLX5_DECAP_EN "decap_en"
+/* Device parameter to configure allow or prevent duplicate rules pattern. */
+#define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
+
/* Shared memory between primary and secondary processes. */
struct mlx5_shared_data *mlx5_shared_data;
.grow_trunk = 3,
.grow_shift = 2,
.need_lock = 1,
- .release_mem_en = 1,
+ .release_mem_en = 0,
+ .per_core_cache = (1 << 16),
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_tag_ipool",
},
#endif
[MLX5_IPOOL_MTR] = {
- .size = sizeof(struct mlx5_flow_meter),
+ /**
+ * The ipool index should grow continually from small to big,
+ * for meter idx, so not set grow_trunk to avoid meter index
+ * not jump continually.
+ */
+ .size = sizeof(struct mlx5_legacy_flow_meter),
.trunk_size = 64,
- .grow_trunk = 3,
- .grow_shift = 2,
.need_lock = 1,
.release_mem_en = 1,
.malloc = mlx5_malloc,
.grow_trunk = 3,
.grow_shift = 2,
.need_lock = 1,
- .release_mem_en = 1,
+ .release_mem_en = 0,
+ .per_core_cache = 1 << 19,
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_flow_handle_ipool",
.free = mlx5_free,
.type = "mlx5_shared_action_rss",
},
+ [MLX5_IPOOL_MTR_POLICY] = {
+ /**
+ * The ipool index should grow continually from small to big,
+ * for policy idx, so not set grow_trunk to avoid policy index
+ * not jump continually.
+ */
+ .size = sizeof(struct mlx5_flow_meter_sub_policy),
+ .trunk_size = 64,
+ .need_lock = 1,
+ .release_mem_en = 1,
+ .malloc = mlx5_malloc,
+ .free = mlx5_free,
+ .type = "mlx5_meter_policy_ipool",
+ },
};
#define MLX5_FLOW_MIN_ID_POOL_SIZE 512
#define MLX5_ID_GENERATION_ARRAY_FACTOR 16
-#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
+#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
+
+/**
+ * Decide whether representor ID is a HPF(host PF) port on BF2.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ *
+ * @return
+ * Non-zero if HPF, otherwise 0.
+ */
+bool
+mlx5_is_hpf(struct rte_eth_dev *dev)
+{
+ struct mlx5_priv *priv = dev->data->dev_private;
+ uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
+ int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
+
+ return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
+ MLX5_REPRESENTOR_REPR(-1) == repr;
+}
+
+/**
+ * Decide whether representor ID is a SF port representor.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ *
+ * @return
+ * Non-zero if HPF, otherwise 0.
+ */
+bool
+mlx5_is_sf_repr(struct rte_eth_dev *dev)
+{
+ struct mlx5_priv *priv = dev->data->dev_private;
+ int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
+
+ return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
+}
/**
* Initialize the ASO aging management structure.
rte_errno = ENOMEM;
return -ENOMEM;
}
- err = mlx5_aso_queue_init(sh);
+ err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
if (err) {
mlx5_free(sh->aso_age_mng);
return -1;
{
int i, j;
- mlx5_aso_queue_stop(sh);
- mlx5_aso_queue_uninit(sh);
+ mlx5_aso_flow_hit_queue_poll_stop(sh);
+ mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
if (sh->aso_age_mng->pools) {
struct mlx5_aso_age_pool *pool;
memset(&sh->cmng, 0, sizeof(sh->cmng));
}
+/**
+ * Initialize the aso flow meters management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free
+ */
+int
+mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
+{
+ if (!sh->mtrmng) {
+ sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
+ sizeof(*sh->mtrmng),
+ RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
+ if (!sh->mtrmng) {
+ DRV_LOG(ERR,
+ "meter management allocation was failed.");
+ rte_errno = ENOMEM;
+ return -ENOMEM;
+ }
+ if (sh->meter_aso_en) {
+ rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
+ LIST_INIT(&sh->mtrmng->pools_mng.meters);
+ }
+ sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
+ }
+ return 0;
+}
+
+/**
+ * Close and release all the resources of
+ * the ASO flow meter management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free.
+ */
+static void
+mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
+{
+ struct mlx5_aso_mtr_pool *mtr_pool;
+ struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
+ uint32_t idx;
+#ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
+ struct mlx5_aso_mtr *aso_mtr;
+ int i;
+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
+
+ if (sh->meter_aso_en) {
+ mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
+ idx = mtrmng->pools_mng.n_valid;
+ while (idx--) {
+ mtr_pool = mtrmng->pools_mng.pools[idx];
+#ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
+ for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
+ aso_mtr = &mtr_pool->mtrs[i];
+ if (aso_mtr->fm.meter_action)
+ claim_zero
+ (mlx5_glue->destroy_flow_action
+ (aso_mtr->fm.meter_action));
+ }
+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
+ claim_zero(mlx5_devx_cmd_destroy
+ (mtr_pool->devx_obj));
+ mtrmng->pools_mng.n_valid--;
+ mlx5_free(mtr_pool);
+ }
+ mlx5_free(sh->mtrmng->pools_mng.pools);
+ }
+ mlx5_free(sh->mtrmng);
+ sh->mtrmng = NULL;
+}
+
/* Send FLOW_AGED event if needed. */
void
mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
age_info = &sh->port[i].age_info;
if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
continue;
- if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
+ MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
+ if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
+ MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
rte_eth_dev_callback_process
(&rte_eth_devices[sh->port[i].devx_ih_port_id],
RTE_ETH_EVENT_FLOW_AGED, NULL);
- age_info->flags = 0;
+ }
}
}
+/*
+ * Initialize the ASO connection tracking structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
+{
+ int err;
+
+ if (sh->ct_mng)
+ return 0;
+ sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
+ RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
+ if (!sh->ct_mng) {
+ DRV_LOG(ERR, "ASO CT management allocation failed.");
+ rte_errno = ENOMEM;
+ return -rte_errno;
+ }
+ err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
+ if (err) {
+ mlx5_free(sh->ct_mng);
+ /* rte_errno should be extracted from the failure. */
+ rte_errno = EINVAL;
+ return -rte_errno;
+ }
+ rte_spinlock_init(&sh->ct_mng->ct_sl);
+ rte_rwlock_init(&sh->ct_mng->resize_rwl);
+ LIST_INIT(&sh->ct_mng->free_cts);
+ return 0;
+}
+
+/*
+ * Close and release all the resources of the
+ * ASO connection tracking management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free.
+ */
+static void
+mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
+{
+ struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
+ struct mlx5_aso_ct_pool *ct_pool;
+ struct mlx5_aso_ct_action *ct;
+ uint32_t idx;
+ uint32_t val;
+ uint32_t cnt;
+ int i;
+
+ mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
+ idx = mng->next;
+ while (idx--) {
+ cnt = 0;
+ ct_pool = mng->pools[idx];
+ for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
+ ct = &ct_pool->actions[i];
+ val = __atomic_fetch_sub(&ct->refcnt, 1,
+ __ATOMIC_RELAXED);
+ MLX5_ASSERT(val == 1);
+ if (val > 1)
+ cnt++;
+#ifdef HAVE_MLX5_DR_ACTION_ASO_CT
+ if (ct->dr_action_orig)
+ claim_zero(mlx5_glue->destroy_flow_action
+ (ct->dr_action_orig));
+ if (ct->dr_action_rply)
+ claim_zero(mlx5_glue->destroy_flow_action
+ (ct->dr_action_rply));
+#endif
+ }
+ claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
+ if (cnt) {
+ DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
+ cnt, i);
+ }
+ mlx5_free(ct_pool);
+ /* in case of failure. */
+ mng->next--;
+ }
+ mlx5_free(mng->pools);
+ mlx5_free(mng);
+ /* Management structure must be cleared to 0s during allocation. */
+ sh->ct_mng = NULL;
+}
+
/**
* Initialize the flow resources' indexed mempool.
*
* @param[in] sh
* Pointer to mlx5_dev_ctx_shared object.
- * @param[in] sh
+ * @param[in] config
* Pointer to user dev config.
*/
static void
MLX5_FLOW_HANDLE_VERBS_SIZE;
break;
}
- if (config->reclaim_mode)
+ if (config->reclaim_mode) {
cfg.release_mem_en = 1;
+ cfg.per_core_cache = 0;
+ } else {
+ cfg.release_mem_en = 0;
+ }
sh->ipool[i] = mlx5_ipool_create(&cfg);
}
}
+
/**
* Release the flow resources' indexed mempool.
*
for (i = 0; i < MLX5_IPOOL_MAX; ++i)
mlx5_ipool_destroy(sh->ipool[i]);
+ for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
+ if (sh->mdh_ipools[i])
+ mlx5_ipool_destroy(sh->mdh_ipools[i]);
}
/*
* the UAR mapping type into account on UAR setup
* on queue creation.
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->tx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* If Verbs/kernel does not support "Non-Cached"
* try the "Write-Combining".
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
sh->tx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
sh->tx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
* should be no datapath noticeable impact,
* can try "Non-Cached" mapping safely.
*/
- DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
sh->devx_rx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
rte_errno = ENOMEM;
goto exit;
}
+ sh->numa_node = spawn->numa_node;
+ if (spawn->bond_info)
+ sh->bond = *spawn->bond_info;
err = mlx5_os_open_device(spawn, config, sh);
if (!sh->ctx)
goto error;
goto error;
}
sh->refcnt = 1;
- sh->bond_dev = UINT16_MAX;
sh->max_port = spawn->max_port;
+ sh->reclaim_mode = config->reclaim_mode;
strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
sizeof(sh->ibdev_name) - 1);
strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
goto error;
}
if (sh->devx) {
- /* Query the EQN for this core. */
- err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
- if (err) {
- rte_errno = errno;
- DRV_LOG(ERR, "Failed to query event queue number %d.",
- rte_errno);
- goto error;
- }
err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
if (err) {
DRV_LOG(ERR, "Fail to extract pdn from PD");
*/
err = mlx5_mr_btree_init(&sh->share_cache.cache,
MLX5_MR_BTREE_CACHE_N * 2,
- spawn->pci_dev->device.numa_node);
+ sh->numa_node);
if (err) {
err = rte_errno;
goto error;
err = rte_errno;
goto error;
}
+ if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
+ err = mlx5_flow_os_init_workspace_once();
+ if (err)
+ goto error;
+ }
mlx5_flow_aging_init(sh);
mlx5_flow_counters_mng_init(sh);
mlx5_flow_ipool_create(sh, config);
rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
/* Add context to the global device list. */
LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
+ rte_spinlock_init(&sh->geneve_tlv_opt_sl);
exit:
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
return sh;
mlx5_mr_release_cache(&sh->share_cache);
/* Remove context from the global device list. */
LIST_REMOVE(sh, next);
+ /* Release flow workspaces objects on the last device. */
+ if (LIST_EMPTY(&mlx5_dev_ctx_list))
+ mlx5_flow_os_release_workspace();
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
/*
* Ensure there is no async event handler installed.
mlx5_flow_aso_age_mng_close(sh);
sh->aso_age_mng = NULL;
}
+ if (sh->mtrmng)
+ mlx5_aso_flow_mtrs_mng_close(sh);
mlx5_flow_ipool_destroy(sh);
mlx5_os_dev_shared_handler_uninstall(sh);
if (sh->cnt_id_tbl) {
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
if (sh->ctx)
claim_zero(mlx5_glue->close_device(sh->ctx));
+ MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
pthread_mutex_destroy(&sh->txpp.mutex);
mlx5_free(sh);
return;
/* Tables are only used in DV and DR modes. */
#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
struct mlx5_dev_ctx_shared *sh = priv->sh;
- char s[MLX5_HLIST_NAMESIZE];
+ char s[MLX5_NAME_SIZE];
MLX5_ASSERT(sh);
snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
- 0, 0, flow_dv_tbl_create_cb,
+ false, true, sh,
+ flow_dv_tbl_create_cb,
flow_dv_tbl_match_cb,
- flow_dv_tbl_remove_cb);
+ flow_dv_tbl_remove_cb,
+ flow_dv_tbl_clone_cb,
+ flow_dv_tbl_clone_free_cb);
if (!sh->flow_tbls) {
DRV_LOG(ERR, "flow tables with hash creation failed.");
err = ENOMEM;
return err;
}
- sh->flow_tbls->ctx = sh;
#ifndef HAVE_MLX5DV_DR
struct rte_flow_error error;
struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
* because DV expect to see them even if they cannot be created by
* RDMA-CORE.
*/
- if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
- !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
- !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
+ if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
+ NULL, 0, 1, 0, &error) ||
+ !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
+ NULL, 0, 1, 0, &error) ||
+ !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
+ NULL, 0, 1, 0, &error)) {
err = ENOMEM;
goto error;
}
struct mlx5_proc_priv *ppriv;
size_t ppriv_size;
+ mlx5_proc_priv_uninit(dev);
/*
* UAR register table follows the process private structure. BlueFlame
* registers for Tx queues are stored in the table.
*/
ppriv_size =
sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
- ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
- dev->device->numa_node);
+ ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
+ RTE_CACHE_LINE_SIZE, dev->device->numa_node);
if (!ppriv) {
rte_errno = ENOMEM;
return -rte_errno;
}
- ppriv->uar_table_sz = ppriv_size;
+ ppriv->uar_table_sz = priv->txqs_n;
dev->process_private = ppriv;
return 0;
}
* @param dev
* Pointer to Ethernet device structure.
*/
-static void
+void
mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
{
if (!dev->process_private)
* If all the flows are already flushed in the device stop stage,
* then this will return directly without any action.
*/
- mlx5_flow_list_flush(dev, &priv->flows, true);
- mlx5_shared_action_flush(dev);
+ mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
+ mlx5_action_handle_flush(dev);
mlx5_flow_meter_flush(dev, NULL);
/* Prevent crashes when queues are still in use. */
dev->rx_pkt_burst = removed_rx_burst;
priv->txqs = NULL;
}
mlx5_proc_priv_uninit(dev);
+ if (priv->q_counters) {
+ mlx5_devx_cmd_destroy(priv->q_counters);
+ priv->q_counters = NULL;
+ }
if (priv->drop_queue.hrxq)
mlx5_drop_action_destroy(dev);
if (priv->mreg_cp_tbl)
mlx5_hlist_destroy(priv->mreg_cp_tbl);
mlx5_mprq_free_mp(dev);
+ if (priv->sh->ct_mng)
+ mlx5_flow_aso_ct_mng_close(priv->sh);
mlx5_os_free_shared_dr(priv);
if (priv->rss_conf.rss_key != NULL)
mlx5_free(priv->rss_conf.rss_key);
if (ret)
DRV_LOG(WARNING, "port %u some flows still remain",
dev->data->port_id);
- mlx5_cache_list_destroy(&priv->hrxqs);
+ if (priv->hrxqs)
+ mlx5_list_destroy(priv->hrxqs);
/*
* Free the shared context in last turn, because the cleanup
* routines above may use some shared fields, like
unsigned int c = 0;
uint16_t port_id;
- MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
+ MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
struct mlx5_priv *opriv =
rte_eth_devices[port_id].data->dev_private;
.xstats_get_names = mlx5_xstats_get_names,
.fw_version_get = mlx5_fw_version_get,
.dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
.read_clock = mlx5_txpp_read_clock,
.dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
.vlan_filter_set = mlx5_vlan_filter_set,
.reta_query = mlx5_dev_rss_reta_query,
.rss_hash_update = mlx5_rss_hash_update,
.rss_hash_conf_get = mlx5_rss_hash_conf_get,
- .filter_ctrl = mlx5_dev_filter_ctrl,
+ .flow_ops_get = mlx5_flow_ops_get,
.rxq_info_get = mlx5_rxq_info_get,
.txq_info_get = mlx5_txq_info_get,
.rx_burst_mode_get = mlx5_rx_burst_mode_get,
.hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
.hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
.hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+ .get_monitor_addr = mlx5_get_monitor_addr,
};
/* Available operations from secondary process. */
.xstats_get_names = mlx5_xstats_get_names,
.fw_version_get = mlx5_fw_version_get,
.dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
.read_clock = mlx5_txpp_read_clock,
.rx_queue_start = mlx5_rx_queue_start,
.rx_queue_stop = mlx5_rx_queue_stop,
.xstats_get_names = mlx5_xstats_get_names,
.fw_version_get = mlx5_fw_version_get,
.dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
.read_clock = mlx5_txpp_read_clock,
.dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
.vlan_filter_set = mlx5_vlan_filter_set,
.mtu_set = mlx5_dev_set_mtu,
.vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
.vlan_offload_set = mlx5_vlan_offload_set,
- .filter_ctrl = mlx5_dev_filter_ctrl,
+ .flow_ops_get = mlx5_flow_ops_get,
.rxq_info_get = mlx5_rxq_info_get,
.txq_info_get = mlx5_txq_info_get,
.rx_burst_mode_get = mlx5_rx_burst_mode_get,
.hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
.hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
.hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+ .get_monitor_addr = mlx5_get_monitor_addr,
};
/**
}
config->cqe_comp = !!tmp;
config->cqe_comp_fmt = tmp;
- } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
- config->cqe_pad = !!tmp;
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
config->max_dump_files_num = tmp;
} else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
config->lro.timeout = tmp;
- } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
+ } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
DRV_LOG(DEBUG, "class argument is %s.", val);
} else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
config->log_hp_size = tmp;
config->sys_mem_en = !!tmp;
} else if (strcmp(MLX5_DECAP_EN, key) == 0) {
config->decap_en = !!tmp;
+ } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
+ config->allow_duplicate_pattern = !!tmp;
} else {
DRV_LOG(WARNING, "%s: unknown parameter", key);
rte_errno = EINVAL;
{
const char **params = (const char *[]){
MLX5_RXQ_CQE_COMP_EN,
- MLX5_RXQ_CQE_PAD_EN,
MLX5_RXQ_PKT_PAD_EN,
MLX5_RX_MPRQ_EN,
MLX5_RX_MPRQ_LOG_STRIDE_NUM,
MLX5_REPRESENTOR,
MLX5_MAX_DUMP_FILES_NUM,
MLX5_LRO_TIMEOUT_USEC,
- MLX5_CLASS_ARG_NAME,
+ RTE_DEVARGS_KEY_CLASS,
MLX5_HP_BUF_SIZE,
MLX5_RECLAIM_MEM,
MLX5_SYS_MEM_EN,
MLX5_DECAP_EN,
+ MLX5_ALLOW_DUPLICATE_PATTERN,
NULL,
};
struct rte_kvargs *kvlist;
{
if (config->txq_inline_min != MLX5_ARG_UNSET) {
/* Application defines size of inlined data explicitly. */
- switch (spawn->pci_dev->id.device_id) {
- case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
- if (config->txq_inline_min <
- (int)MLX5_INLINE_HSIZE_L2) {
- DRV_LOG(DEBUG,
- "txq_inline_mix aligned to minimal"
- " ConnectX-4 required value %d",
- (int)MLX5_INLINE_HSIZE_L2);
- config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
+ if (spawn->pci_dev != NULL) {
+ switch (spawn->pci_dev->id.device_id) {
+ case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
+ case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
+ if (config->txq_inline_min <
+ (int)MLX5_INLINE_HSIZE_L2) {
+ DRV_LOG(DEBUG,
+ "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
+ (int)MLX5_INLINE_HSIZE_L2);
+ config->txq_inline_min =
+ MLX5_INLINE_HSIZE_L2;
+ }
+ break;
}
- break;
}
goto exit;
}
}
}
}
+ if (spawn->pci_dev == NULL) {
+ config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
+ goto exit;
+ }
/*
* We get here if we are unable to deduce
* inline data size with DevX. Try PCI ID
if (sh->refcnt == 1)
return 0;
/* Find the device with shared context. */
- MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
+ MLX5_ETH_FOREACH_DEV(port_id, NULL) {
struct mlx5_priv *opriv =
rte_eth_devices[port_id].data->dev_private;
*
* @param[in] port_id
* port_id to start looking for device.
- * @param[in] pci_dev
- * Pointer to the hint PCI device. When device is being probed
+ * @param[in] odev
+ * Pointer to the hint device. When device is being probed
* the its siblings (master and preceding representors might
* not have assigned driver yet (because the mlx5_os_pci_probe()
- * is not completed yet, for this case match on hint PCI
+ * is not completed yet, for this case match on hint
* device may be used to detect sibling device.
*
* @return
* port_id of found device, RTE_MAX_ETHPORT if not found.
*/
uint16_t
-mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
+mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
{
while (port_id < RTE_MAX_ETHPORTS) {
struct rte_eth_dev *dev = &rte_eth_devices[port_id];
if (dev->state != RTE_ETH_DEV_UNUSED &&
dev->device &&
- (dev->device == &pci_dev->device ||
+ (dev->device == odev ||
(dev->device->driver &&
dev->device->driver->name &&
- !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
+ ((strcmp(dev->device->driver->name,
+ MLX5_PCI_DRIVER_NAME) == 0) ||
+ (strcmp(dev->device->driver->name,
+ MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
break;
port_id++;
}
}
/**
- * DPDK callback to remove a PCI device.
+ * Callback to remove a device.
*
- * This function removes all Ethernet devices belong to a given PCI device.
+ * This function removes all Ethernet devices belong to a given device.
*
- * @param[in] pci_dev
- * Pointer to the PCI device.
+ * @param[in] dev
+ * Pointer to the generic device.
*
* @return
* 0 on success, the function cannot fail.
*/
static int
-mlx5_pci_remove(struct rte_pci_device *pci_dev)
+mlx5_net_remove(struct rte_device *dev)
{
uint16_t port_id;
int ret = 0;
- RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
+ RTE_ETH_FOREACH_DEV_OF(port_id, dev) {
/*
* mlx5_dev_close() is not registered to secondary process,
* call the close function explicitly for secondary process.
}
};
-static struct mlx5_pci_driver mlx5_driver = {
- .driver_class = MLX5_CLASS_NET,
- .pci_driver = {
- .driver = {
- .name = MLX5_DRIVER_NAME,
- },
- .id_table = mlx5_pci_id_map,
- .probe = mlx5_os_pci_probe,
- .remove = mlx5_pci_remove,
- .dma_map = mlx5_dma_map,
- .dma_unmap = mlx5_dma_unmap,
- .drv_flags = PCI_DRV_FLAGS,
- },
+static struct mlx5_class_driver mlx5_net_driver = {
+ .drv_class = MLX5_CLASS_ETH,
+ .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
+ .id_table = mlx5_pci_id_map,
+ .probe = mlx5_os_net_probe,
+ .remove = mlx5_net_remove,
+ .dma_map = mlx5_net_dma_map,
+ .dma_unmap = mlx5_net_dma_unmap,
+ .probe_again = 1,
+ .intr_lsc = 1,
+ .intr_rmv = 1,
};
/* Initialize driver log type. */
-RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
+RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
/**
* Driver initialization routine.
mlx5_set_cksum_table();
mlx5_set_swp_types_table();
if (mlx5_glue)
- mlx5_pci_driver_register(&mlx5_driver);
+ mlx5_class_driver_register(&mlx5_net_driver);
}
-RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
-RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
-RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
+RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
+RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
+RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");
git.droids-corp.org / dpdk.git / blobdiff