net/mlx5: fix comment

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 92daf86..1f279dc 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -195,12 +195,6 @@ TAILQ_HEAD(mlx5_flows, rte_flow);
 #define MLX5_LRO_SUPPORTED(dev) \
        (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
 
-#define MLX5_LRO_ENABLED(dev) \
-       ((dev)->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
-
-#define MLX5_FLOW_IPV4_LRO     (1 << 0)
-#define MLX5_FLOW_IPV6_LRO     (1 << 1)
-
 /* LRO configurations structure. */
 struct mlx5_lro_config {
        uint32_t supported:1; /* Whether LRO is supported. */
@@ -361,6 +355,30 @@ enum mlx5_verbs_alloc_type {
        MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
 };
 
+/* VLAN netdev for VLAN workaround. */
+struct mlx5_vlan_dev {
+       uint32_t refcnt;
+       uint32_t ifindex; /**< Own interface index. */
+};
+
+/* Structure for VF VLAN workaround. */
+struct mlx5_vf_vlan {
+       uint32_t tag:12;
+       uint32_t created:1;
+};
+
+/*
+ * Array of VLAN devices created on the base of VF
+ * used for workaround in virtual environments.
+ */
+struct mlx5_vlan_vmwa_context {
+       int nl_socket;
+       uint32_t nl_sn;
+       uint32_t vf_ifindex;
+       struct rte_eth_dev *dev;
+       struct mlx5_vlan_dev vlan_dev[4096];
+};
+
 /**
  * Verbs allocator needs a context to know in the callback which kind of
  * resources it is allocating.
@@ -375,7 +393,7 @@ LIST_HEAD(mlx5_mr_list, mlx5_mr);
 /* Flow drop context necessary due to Verbs API. */
 struct mlx5_drop {
        struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
-       struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
+       struct mlx5_rxq_obj *rxq; /* Rx queue object. */
 };
 
 #define MLX5_COUNTERS_PER_POOL 512
@@ -495,8 +513,8 @@ struct mlx5_flow_tbl_resource {
        rte_atomic32_t refcnt; /**< Reference counter. */
 };
 
-#define MLX5_MAX_TABLES 1024
-#define MLX5_MAX_TABLES_FDB 32
+#define MLX5_MAX_TABLES 0xffff
+#define MLX5_MAX_TABLES_FDB 0xffff
 #define MLX5_GROUP_FACTOR 1
 
 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
@@ -525,6 +543,7 @@ struct mlx5_ibv_shared {
        uint32_t max_port; /* Maximal IB device port index. */
        struct ibv_context *ctx; /* Verbs/DV context. */
        struct ibv_pd *pd; /* Protection Domain. */
+       uint32_t pdn; /* Protection Domain number. */
        uint32_t tdn; /* Transport Domain number. */
        char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
        char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
@@ -550,8 +569,8 @@ struct mlx5_ibv_shared {
        /* RX Direct Rules tables. */
        void *tx_domain; /* TX Direct Rules name space handle. */
        struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
+       /* TX Direct Rules tables. */
        void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
-       /* TX Direct Rules tables/ */
        LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
        LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
        LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
@@ -613,17 +632,18 @@ struct mlx5_priv {
        struct mlx5_flows flows; /* RTE Flow rules. */
        struct mlx5_flows ctrl_flows; /* Control flow rules. */
        LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
-       LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
+       LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
        LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
        LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
        LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
-       /* Verbs Indirection tables. */
-       LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
+       /* Indirection tables. */
+       LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
        /* Pointer to next element. */
        rte_atomic32_t refcnt; /**< Reference counter. */
        struct ibv_flow_action *verbs_action;
        /**< Verbs modify header action object. */
        uint8_t ft_type; /**< Flow table type, Rx or Tx. */
+       uint8_t max_lro_msg_size;
        /* Tags resources cache. */
        uint32_t link_speed_capa; /* Link speed capabilities. */
        struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
@@ -635,6 +655,7 @@ struct mlx5_priv {
        int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
        uint32_t nl_sn; /* Netlink message sequence number. */
        LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
+       struct mlx5_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
 #ifndef RTE_ARCH_64
        rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
        rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
@@ -834,6 +855,14 @@ unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
                        struct mlx5_switch_info *info);
 
+struct mlx5_vlan_vmwa_context *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev,
+                                                  uint32_t ifindex);
+void mlx5_vlan_vmwa_exit(struct mlx5_vlan_vmwa_context *ctx);
+void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
+                           struct mlx5_vf_vlan *vf_vlan);
+void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
+                           struct mlx5_vf_vlan *vf_vlan);
+
 /* mlx5_devx_cmds.c */
 
 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,