net/mlx5: create advanced RxQ object via DevX

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 5fe3cf9..4f4c4a7 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -165,6 +165,9 @@ struct mlx5_devx_mkey_attr {
        uint32_t pd;
 };
 
+/* HCA supports this number of time periods for LRO. */
+#define MLX5_LRO_NUM_SUPP_PERIODS 4
+
 /* HCA attributes. */
 struct mlx5_hca_attr {
        uint32_t eswitch_manager:1;
@@ -175,6 +178,11 @@ struct mlx5_hca_attr {
        uint32_t wqe_vlan_insert:1;
        uint32_t wqe_inline_mode:2;
        uint32_t vport_inline_mode:3;
+       uint32_t lro_cap:1;
+       uint32_t tunnel_lro_gre:1;
+       uint32_t tunnel_lro_vxlan:1;
+       uint32_t lro_max_msg_sz_mode:2;
+       uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
 };
 
 /* Flow list . */
@@ -183,6 +191,21 @@ TAILQ_HEAD(mlx5_flows, rte_flow);
 /* Default PMD specific parameter value. */
 #define MLX5_ARG_UNSET (-1)
 
+#define MLX5_LRO_SUPPORTED(dev) \
+       (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
+
+#define MLX5_LRO_ENABLED(dev) \
+       ((dev)->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
+
+#define MLX5_FLOW_IPV4_LRO     (1 << 0)
+#define MLX5_FLOW_IPV6_LRO     (1 << 1)
+
+/* LRO configurations structure. */
+struct mlx5_lro_config {
+       uint32_t supported:1; /* Whether LRO is supported. */
+       uint32_t timeout; /* User configuration. */
+};
+
 /*
  * Device configuration structure.
  *
@@ -213,6 +236,7 @@ struct mlx5_dev_config {
        unsigned int dv_flow_en:1; /* Enable DV flow. */
        unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
        unsigned int devx:1; /* Whether devx interface is available or not. */
+       unsigned int dest_tir:1; /* Whether advanced DR API is available. */
        struct {
                unsigned int enabled:1; /* Whether MPRQ is enabled. */
                unsigned int stride_num_n; /* Number of strides. */
@@ -233,6 +257,53 @@ struct mlx5_dev_config {
        int txq_inline_max; /* Max packet size for inlining with SEND. */
        int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
        struct mlx5_hca_attr hca_attr; /* HCA attributes. */
+       struct mlx5_lro_config lro; /* LRO configuration. */
+};
+
+struct mlx5_devx_wq_attr {
+       uint32_t wq_type:4;
+       uint32_t wq_signature:1;
+       uint32_t end_padding_mode:2;
+       uint32_t cd_slave:1;
+       uint32_t hds_skip_first_sge:1;
+       uint32_t log2_hds_buf_size:3;
+       uint32_t page_offset:5;
+       uint32_t lwm:16;
+       uint32_t pd:24;
+       uint32_t uar_page:24;
+       uint64_t dbr_addr;
+       uint32_t hw_counter;
+       uint32_t sw_counter;
+       uint32_t log_wq_stride:4;
+       uint32_t log_wq_pg_sz:5;
+       uint32_t log_wq_sz:5;
+       uint32_t dbr_umem_valid:1;
+       uint32_t wq_umem_valid:1;
+       uint32_t log_hairpin_num_packets:5;
+       uint32_t log_hairpin_data_sz:5;
+       uint32_t single_wqe_log_num_of_strides:4;
+       uint32_t two_byte_shift_en:1;
+       uint32_t single_stride_log_num_of_bytes:3;
+       uint32_t dbr_umem_id;
+       uint32_t wq_umem_id;
+       uint64_t wq_umem_offset;
+};
+
+/* Create RQ attributes structure, used by create RQ operation. */
+struct mlx5_devx_create_rq_attr {
+       uint32_t rlky:1;
+       uint32_t delay_drop_en:1;
+       uint32_t scatter_fcs:1;
+       uint32_t vsd:1;
+       uint32_t mem_rq_type:4;
+       uint32_t state:4;
+       uint32_t flush_in_error_en:1;
+       uint32_t hairpin:1;
+       uint32_t user_index:24;
+       uint32_t cqn:24;
+       uint32_t counter_set_id:8;
+       uint32_t rmpn:24;
+       struct mlx5_devx_wq_attr wq_attr;
 };
 
 /**
@@ -393,6 +464,7 @@ struct mlx5_ibv_shared {
        uint32_t max_port; /* Maximal IB device port index. */
        struct ibv_context *ctx; /* Verbs/DV context. */
        struct ibv_pd *pd; /* Protection Domain. */
+       uint32_t tdn; /* Transport Domain number. */
        char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
        char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
        struct ibv_device_attr_ex device_attr; /* Device properties. */
@@ -519,15 +591,9 @@ int mlx5_proc_priv_init(struct rte_eth_dev *dev);
 /* mlx5_ethdev.c */
 
 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
-int mlx5_get_ifname_base(const struct rte_eth_dev *base,
-                        const struct rte_eth_dev *dev,
-                        char (*ifname)[IF_NAMESIZE]);
 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
-int mlx5_ifreq_base(const struct rte_eth_dev *base,
-                   const struct rte_eth_dev *dev,
-                   int req, struct ifreq *ifr);
 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
                   unsigned int flags);
@@ -718,4 +784,10 @@ int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
                                             struct mlx5_devx_mkey_attr *attr);
 int mlx5_devx_get_out_command_status(void *out);
+int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
+                                 uint32_t *tis_td);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
+                               struct mlx5_devx_create_rq_attr *rq_attr,
+                               int socket);
+
 #endif /* RTE_PMD_MLX5_H_ */