MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
+ MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
+ MLX5_IPOOL_TUNNEL_ID, /* Pool for flow tunnel ID. */
+ MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
MLX5_IPOOL_MAX,
};
MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
};
+/* Hash and cache list callback context. */
+struct mlx5_flow_cb_ctx {
+ struct rte_eth_dev *dev;
+ struct rte_flow_error *error;
+ void *data;
+};
+
/* Device attributes used in mlx5 PMD */
struct mlx5_dev_attr {
uint64_t device_cap_flags_ex;
struct mlx5_flow_counter_pool {
TAILQ_ENTRY(mlx5_flow_counter_pool) next;
struct mlx5_counters counters[2]; /* Free counter list. */
- union {
- struct mlx5_devx_obj *min_dcs;
- rte_atomic64_t a64_dcs;
- };
+ struct mlx5_devx_obj *min_dcs;
/* The devx object of the minimum counter ID. */
uint64_t time_of_last_age_check;
/* System time (from rte_rdtsc()) read in the last aging check. */
LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
};
-/* Default miss action resource structure. */
-struct mlx5_flow_default_miss_resource {
- void *action; /* Pointer to the rdma-core action. */
- rte_atomic32_t refcnt; /* Default miss action reference counter. */
-};
-
#define MLX5_AGE_EVENT_NEW 1
#define MLX5_AGE_TRIGGER 2
#define MLX5_AGE_SET(age_info, BIT) \
struct {
/* Table ID should be at the lowest address. */
uint32_t table_id; /**< ID of the table. */
- uint16_t reserved; /**< must be zero for comparison. */
+ uint16_t dummy; /**< Dummy table for DV API. */
uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
uint8_t direction; /**< 1 - egress, 0 - ingress. */
};
/* Table structure. */
struct mlx5_flow_tbl_resource {
void *obj; /**< Pointer to DR table object. */
- rte_atomic32_t refcnt; /**< Reference counter. */
+ uint32_t refcnt; /**< Reference counter. */
};
#define MLX5_MAX_TABLES UINT16_MAX
uint32_t sample_action_list; /* List of sample actions. */
uint32_t dest_array_list; /* List of destination array actions. */
struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
- struct mlx5_flow_default_miss_resource default_miss;
- /* Default miss action resource structure. */
+ void *default_miss_action; /* Default miss action. */
struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
/* Memory Pool for mlx5 flow resources. */
struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
void *devx_comp; /* DEVX async comp obj. */
struct mlx5_devx_obj *tis; /* TIS object. */
struct mlx5_devx_obj *td; /* Transport domain. */
- struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
void *tx_uar; /* Tx/packet pacing shared UAR. */
struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
/* Flex parser profiles information. */
/* MTR list. */
TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
+/* RSS description. */
+struct mlx5_flow_rss_desc {
+ uint32_t level;
+ uint32_t queue_num; /**< Number of entries in @p queue. */
+ uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
+ uint64_t hash_fields; /* Verbs Hash fields. */
+ uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
+ uint32_t key_len; /**< RSS hash key len. */
+ uint32_t tunnel; /**< Queue in tunnel. */
+ union {
+ uint16_t *queue; /**< Destination queues. */
+ const uint16_t *const_q; /**< Const pointer convert. */
+ };
+ bool standalone; /**< Queue is standalone or not. */
+};
+
#define MLX5_PROC_PRIV(port_id) \
((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
/* Hash Rx queue. */
__extension__
struct mlx5_hrxq {
- ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
+ struct mlx5_cache_entry entry; /* Cache entry. */
uint32_t refcnt; /* Reference counter. */
- uint32_t shared:1; /* This object used in shared action. */
+ uint32_t standalone:1; /* This object used in shared action. */
struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
RTE_STD_C11
union {
#endif
uint64_t hash_fields; /* Verbs Hash fields. */
uint32_t rss_key_len; /* Hash key length in bytes. */
+ uint32_t idx; /* Hash Rx queue index. */
uint8_t rss_key[]; /* Hash key. */
};
struct mlx5_drop drop_queue; /* Flow drop queues. */
uint32_t flows; /* RTE Flow rules. */
uint32_t ctrl_flows; /* Control flow rules. */
- void *inter_flows; /* Intermediate resources for flow creation. */
- void *rss_desc; /* Intermediate rss description resources. */
- int flow_idx; /* Intermediate device flow index. */
- int flow_nested_idx; /* Intermediate device flow index, nested. */
+ rte_spinlock_t flow_list_lock;
struct mlx5_obj_ops obj_ops; /* HW objects operations. */
LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
- uint32_t hrxqs; /* Verbs Hash Rx queues. */
+ struct mlx5_cache_list hrxqs; /* Hash Rx queues. */
LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
/* Indirection tables. */
int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
- struct mlx5_flow_id_pool *qrss_id_pool;
struct mlx5_hlist *mreg_cp_tbl;
/* Hash table of Rx metadata register copy table. */
uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
enum rte_filter_type filter_type,
enum rte_filter_op filter_op,
void *arg);
-int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
-void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
int mlx5_flow_start_default(struct rte_eth_dev *dev);
void mlx5_flow_stop_default(struct rte_eth_dev *dev);
-void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
-void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
int mlx5_flow_verify(struct rte_eth_dev *dev);
int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
git.droids-corp.org / dpdk.git / blobdiff