net/mlx5: add new memory region support

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index f1294c5..b2ed990 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -26,12 +26,13 @@
 #include <rte_pci.h>
 #include <rte_ether.h>
 #include <rte_ethdev_driver.h>
-#include <rte_spinlock.h>
+#include <rte_rwlock.h>
 #include <rte_interrupts.h>
 #include <rte_errno.h>
 #include <rte_flow.h>
 
 #include "mlx5_utils.h"
+#include "mlx5_mr.h"
 #include "mlx5_rxtx.h"
 #include "mlx5_autoconf.h"
 #include "mlx5_defs.h"
@@ -51,6 +52,16 @@ enum {
        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
 };
 
+LIST_HEAD(mlx5_dev_list, priv);
+
+/* Shared memory between primary and secondary processes. */
+struct mlx5_shared_data {
+       struct mlx5_dev_list mem_event_cb_list;
+       rte_rwlock_t mem_event_rwlock;
+};
+
+extern struct mlx5_shared_data *mlx5_shared_data;
+
 struct mlx5_xstats_ctrl {
        /* Number of device stats. */
        uint16_t stats_n;
@@ -120,7 +131,10 @@ struct mlx5_verbs_alloc_ctx {
        const void *obj; /* Pointer to the DPDK object. */
 };
 
+LIST_HEAD(mlx5_mr_list, mlx5_mr);
+
 struct priv {
+       LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
        struct rte_eth_dev_data *dev_data;  /* Pointer to device data. */
        struct ibv_context *ctx; /* Verbs context. */
        struct ibv_device_attr_ex device_attr; /* Device properties. */
@@ -147,7 +161,13 @@ struct priv {
        struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
        struct mlx5_flows flows; /* RTE Flow rules. */
        struct mlx5_flows ctrl_flows; /* Control flow rules. */
-       LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
+       struct {
+               uint32_t dev_gen; /* Generation number to flush local caches. */
+               rte_rwlock_t rwlock; /* MR Lock. */
+               struct mlx5_mr_btree cache; /* Global MR cache table. */
+               struct mlx5_mr_list mr_list; /* Registered MR list. */
+               struct mlx5_mr_list mr_free_list; /* Freed MR list. */
+       } mr;
        LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
        LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
        LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
@@ -157,7 +177,6 @@ struct priv {
        LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
        uint32_t link_speed_capa; /* Link speed capabilities. */
        struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
-       rte_spinlock_t mr_lock; /* MR Lock. */
        int primary_socket; /* Unix socket for primary process. */
        void *uar_base; /* Reserved address space for UAR mapping */
        struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
@@ -309,13 +328,6 @@ void mlx5_socket_uninit(struct rte_eth_dev *priv);
 void mlx5_socket_handle(struct rte_eth_dev *priv);
 int mlx5_socket_connect(struct rte_eth_dev *priv);
 
-/* mlx5_mr.c */
-
-struct mlx5_mr *mlx5_mr_new(struct rte_eth_dev *dev, struct rte_mempool *mp);
-struct mlx5_mr *mlx5_mr_get(struct rte_eth_dev *dev, struct rte_mempool *mp);
-int mlx5_mr_release(struct mlx5_mr *mr);
-int mlx5_mr_verify(struct rte_eth_dev *dev);
-
 /* mlx5_nl.c */
 
 int mlx5_nl_init(uint32_t nlgroups);