MLX5_RTE_FLOW_ACTION_TYPE_TAG,
MLX5_RTE_FLOW_ACTION_TYPE_MARK,
MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
+ MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
};
/* Matches on selected register. */
#define MLX5_FLOW_ACTION_METER (1ull << 31)
#define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
#define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
+#define MLX5_FLOW_ACTION_AGE (1ull << 34)
+#define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
#define MLX5_FLOW_FATE_ACTIONS \
(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
- MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
+ MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
+ MLX5_FLOW_ACTION_DEFAULT_MISS)
#define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
#define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
sizeof(struct rte_flow_item_ipv4))
+/* Software header modify action numbers of a flow. */
+#define MLX5_ACT_NUM_MDF_IPV4 1
+#define MLX5_ACT_NUM_MDF_IPV6 4
+#define MLX5_ACT_NUM_MDF_MAC 2
+#define MLX5_ACT_NUM_MDF_VID 1
+#define MLX5_ACT_NUM_MDF_PORT 2
+#define MLX5_ACT_NUM_MDF_TTL 1
+#define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
+#define MLX5_ACT_NUM_MDF_TCPSEQ 1
+#define MLX5_ACT_NUM_MDF_TCPACK 1
+#define MLX5_ACT_NUM_SET_REG 1
+#define MLX5_ACT_NUM_SET_TAG 1
+#define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
+#define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
+#define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
+#define MLX5_ACT_NUM_SET_DSCP 1
+
enum mlx5_flow_drv_type {
MLX5_FLOW_TYPE_MIN,
MLX5_FLOW_TYPE_DV,
MLX5_FLOW_FATE_JUMP,
MLX5_FLOW_FATE_PORT_ID,
MLX5_FLOW_FATE_DROP,
+ MLX5_FLOW_FATE_DEFAULT_MISS,
MLX5_FLOW_FATE_MAX,
};
/*
* Number of modification commands.
- * If extensive metadata registers are supported, the maximal actions amount is
- * 16 and 8 otherwise on root table. The validation could also be done in the
- * lower driver layer.
- * On non-root table, there is no limitation, but 32 is enough right now.
+ * The maximal actions amount in FW is some constant, and it is 16 in the
+ * latest releases. In some old releases, it will be limited to 8.
+ * Since there is no interface to query the capacity, the maximal value should
+ * be used to allow PMD to create the flow. The validation will be done in the
+ * lower driver layer or FW. A failure will be returned if exceeds the maximal
+ * supported actions number on the root table.
+ * On non-root tables, there is no limitation, but 32 is enough right now.
*/
#define MLX5_MAX_MODIFY_NUM 32
#define MLX5_ROOT_TBL_MODIFY_NUM 16
-#define MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG 8
/* Modify resource structure */
struct mlx5_flow_dv_modify_hdr_resource {
/* List entry for device flows. */
uint32_t refcnt; /* Reference counter. */
uint32_t appcnt; /* Apply/Remove counter. */
- struct rte_flow *flow; /* Built flow for copy. */
+ uint32_t idx;
+ uint32_t rix_flow; /* Built flow for copy. */
};
/* Table data structure of the hash organization. */
uint16_t size;
};
-struct mlx5_flow_rss {
+/* RSS description. */
+struct mlx5_flow_rss_desc {
uint32_t level;
uint32_t queue_num; /**< Number of entries in @p queue. */
uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
- uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
+ uint16_t queue[]; /**< Destination queues to redirect traffic to. */
};
+
/** Device flow handle structure for DV mode only. */
struct mlx5_flow_handle_dv {
/* Flow DV api: */
/**< Index to next device flow handle. */
uint64_t layers;
/**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
- void *ib_flow; /**< Verbs flow pointer. */
+ void *drv_flow; /**< pointer to driver flow object. */
uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
uint32_t mark:1; /**< Metadate rxq mark flag. */
uint32_t fate_action:3; /**< Fate action type. */
/**< Index to port ID action resource. */
uint32_t rix_fate;
/**< Generic value indicates the fate action. */
+ uint32_t rix_default_fate;
+ /**< Indicates default miss fate action. */
};
#ifdef HAVE_IBV_FLOW_DV_SUPPORT
struct mlx5_flow_handle_dv dvh;
/** Device flow structure. */
struct mlx5_flow {
struct rte_flow *flow; /**< Pointer to the main flow. */
+ uint32_t flow_idx; /**< The memory pool index to the main flow. */
uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
uint64_t act_flags;
/**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
struct mlx5_flow_meter {
TAILQ_ENTRY(mlx5_flow_meter) next;
/**< Pointer to the next flow meter structure. */
+ uint32_t idx; /* Index to meter object. */
uint32_t meter_id;
/**< Meter id. */
- struct rte_mtr_params params;
- /**< Meter rule parameters. */
struct mlx5_flow_meter_profile *profile;
/**< Meter profile parameters. */
- struct rte_flow_attr attr;
- /**< Flow attributes. */
+
+ /** Policer actions (per meter output color). */
+ enum rte_mtr_policer_action action[RTE_COLORS];
+
+ /** Set of stats counters to be enabled.
+ * @see enum rte_mtr_stats_type
+ */
+ uint64_t stats_mask;
+
+ /**< Rule applies to ingress traffic. */
+ uint32_t ingress:1;
+
+ /**< Rule applies to egress traffic. */
+ uint32_t egress:1;
+ /**
+ * Instead of simply matching the properties of traffic as it would
+ * appear on a given DPDK port ID, enabling this attribute transfers
+ * a flow rule to the lowest possible level of any device endpoints
+ * found in the pattern.
+ *
+ * When supported, this effectively enables an application to
+ * re-route traffic not necessarily intended for it (e.g. coming
+ * from or addressed to different physical ports, VFs or
+ * applications) at the device level.
+ *
+ * It complements the behavior of some pattern items such as
+ * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
+ *
+ * When transferring flow rules, ingress and egress attributes keep
+ * their original meaning, as if processing traffic emitted or
+ * received by the application.
+ */
+ uint32_t transfer:1;
struct mlx5_meter_domains_infos *mfts;
/**< Flow table created for this meter. */
struct mlx5_flow_policer_stats policer_stats;
uint32_t ref_cnt; /**< Use count. */
};
+/* Fdir flow structure */
+struct mlx5_fdir_flow {
+ LIST_ENTRY(mlx5_fdir_flow) next; /* Pointer to the next element. */
+ struct mlx5_fdir *fdir; /* Pointer to fdir. */
+ uint32_t rix_flow; /* Index to flow. */
+};
+
+#define HAIRPIN_FLOW_ID_BITS 28
+
/* Flow structure. */
struct rte_flow {
- TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
- enum mlx5_flow_drv_type drv_type; /**< Driver type. */
- struct mlx5_flow_rss rss; /**< RSS context. */
- uint32_t counter; /**< Holds flow counter. */
- struct mlx5_flow_mreg_copy_resource *mreg_copy;
- /**< pointer to metadata register copy table resource. */
- struct mlx5_flow_meter *meter; /**< Holds flow meter. */
+ ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
uint32_t dev_handles;
/**< Device flow handles that are part of the flow. */
- struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
- uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */
+ uint32_t drv_type:2; /**< Driver type. */
+ uint32_t fdir:1; /**< Identifier of associated FDIR if any. */
+ uint32_t hairpin_flow_id:HAIRPIN_FLOW_ID_BITS;
+ /**< The flow id used for hairpin. */
uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */
-};
+ uint32_t rix_mreg_copy;
+ /**< Index to metadata register copy table resource. */
+ uint32_t counter; /**< Holds flow counter. */
+ uint16_t meter; /**< Holds flow meter id. */
+} __rte_packed;
typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
const struct rte_flow_attr *attr,
const struct rte_flow_item items[],
const struct rte_flow_action actions[],
bool external,
+ int hairpin,
struct rte_flow_error *error);
typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
uint32_t cnt,
bool clear, uint64_t *pkts,
uint64_t *bytes);
+typedef int (*mlx5_flow_get_aged_flows_t)
+ (struct rte_eth_dev *dev,
+ void **context,
+ uint32_t nb_contexts,
+ struct rte_flow_error *error);
struct mlx5_flow_driver_ops {
mlx5_flow_validate_t validate;
mlx5_flow_prepare_t prepare;
mlx5_flow_counter_alloc_t counter_alloc;
mlx5_flow_counter_free_t counter_free;
mlx5_flow_counter_query_t counter_query;
+ mlx5_flow_get_aged_flows_t get_aged_flows;
};
-
-#define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
- [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
-#define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
- [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
-
/* mlx5_flow.c */
struct mlx5_flow_id_pool *mlx5_flow_id_pool_alloc(uint32_t max_id);
int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
bool external, uint32_t group, bool fdb_def_rule,
uint32_t *table, struct rte_flow_error *error);
-uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
- uint64_t layer_types,
+uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
+ int tunnel, uint64_t layer_types,
uint64_t hash_fields);
uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
uint32_t subpriority);
const struct rte_flow_attr *attr,
uint64_t item_flags,
struct rte_flow_error *error);
+int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
+ const struct rte_flow_attr *attr,
+ struct rte_flow_error *error);
int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
const struct rte_flow_attr *attributes,
struct rte_flow_error *error);
git.droids-corp.org / dpdk.git / blobdiff