#define MLX5_FLOW_ITEM_MARK (1u << 19)
/* Pattern MISC bits. */
-#define MLX5_FLOW_LAYER_ICMP (1u << 19)
-#define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
-#define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
+#define MLX5_FLOW_LAYER_ICMP (1u << 20)
+#define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
/* Pattern tunnel Layer bits (continued). */
-#define MLX5_FLOW_LAYER_IPIP (1u << 21)
-#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
-#define MLX5_FLOW_LAYER_NVGRE (1u << 23)
-#define MLX5_FLOW_LAYER_GENEVE (1u << 24)
+#define MLX5_FLOW_LAYER_IPIP (1u << 23)
+#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
+#define MLX5_FLOW_LAYER_NVGRE (1u << 25)
+#define MLX5_FLOW_LAYER_GENEVE (1u << 26)
/* Queue items. */
-#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
+#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
+
+/* Pattern tunnel Layer bits (continued). */
+#define MLX5_FLOW_LAYER_GTP (1u << 28)
/* Outer Masks. */
#define MLX5_FLOW_LAYER_OUTER_L3 \
(MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
MLX5_FLOW_LAYER_OUTER_L4)
-/* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
-#define MLX5_FLOW_LAYER_IPV4_LRO \
- (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
-#define MLX5_FLOW_LAYER_IPV6_LRO \
- (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
-
/* Tunnel Masks. */
#define MLX5_FLOW_LAYER_TUNNEL \
(MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
- MLX5_FLOW_LAYER_GENEVE)
+ MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
/* Inner Masks. */
#define MLX5_FLOW_LAYER_INNER_L3 \
#define MLX5_FLOW_ACTION_MARK_EXT (1ull << 33)
#define MLX5_FLOW_ACTION_SET_META (1ull << 34)
#define MLX5_FLOW_ACTION_METER (1ull << 35)
+#define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 36)
+#define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 37)
#define MLX5_FLOW_FATE_ACTIONS \
(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
MLX5_FLOW_ACTION_SET_TAG | \
MLX5_FLOW_ACTION_MARK_EXT | \
- MLX5_FLOW_ACTION_SET_META)
+ MLX5_FLOW_ACTION_SET_META | \
+ MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
+ MLX5_FLOW_ACTION_SET_IPV6_DSCP)
#define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
MLX5_FLOW_ACTION_OF_PUSH_VLAN)
/* IBV hash source bits for IPV6. */
#define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
+/* IBV hash bits for L3 SRC. */
+#define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
+
+/* IBV hash bits for L3 DST. */
+#define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
+
+/* IBV hash bits for TCP. */
+#define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
+ IBV_RX_HASH_DST_PORT_TCP)
+
+/* IBV hash bits for UDP. */
+#define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
+ IBV_RX_HASH_DST_PORT_UDP)
+
+/* IBV hash bits for L4 SRC. */
+#define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
+ IBV_RX_HASH_SRC_PORT_UDP)
+
+/* IBV hash bits for L4 DST. */
+#define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
+ IBV_RX_HASH_DST_PORT_UDP)
/* Geneve header first 16Bit */
#define MLX5_GENEVE_VER_MASK 0x3
/* Matcher structure. */
struct mlx5_flow_dv_matcher {
LIST_ENTRY(mlx5_flow_dv_matcher) next;
- /* Pointer to the next element. */
+ /**< Pointer to the next element. */
+ struct mlx5_flow_tbl_resource *tbl;
+ /**< Pointer to the table(group) the matcher associated with. */
rte_atomic32_t refcnt; /**< Reference counter. */
void *matcher_object; /**< Pointer to DV matcher */
uint16_t crc; /**< CRC of key. */
uint16_t priority; /**< Priority of matcher. */
- uint8_t egress; /**< Egress matcher. */
- uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
- uint32_t group; /**< The matcher group. */
struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
};
/* Tag resource structure. */
struct mlx5_flow_dv_tag_resource {
- LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
- /* Pointer to next element. */
- rte_atomic32_t refcnt; /**< Reference counter. */
+ struct mlx5_hlist_entry entry;
+ /**< hash list entry for tag resource, tag value as the key. */
void *action;
/**< Verbs tag action object. */
- uint32_t tag; /**< the tag value. */
+ rte_atomic32_t refcnt; /**< Reference counter. */
};
/*
/* Jump action resource structure. */
struct mlx5_flow_dv_jump_tbl_resource {
- LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
- /* Pointer to next element. */
rte_atomic32_t refcnt; /**< Reference counter. */
- void *action; /**< Pointer to the rdma core action. */
uint8_t ft_type; /**< Flow table type, Rx or Tx. */
- struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
+ void *action; /**< Pointer to the rdma core action. */
};
/* Port ID resource structure. */
struct rte_flow *flow; /* Built flow for copy. */
};
+/* Table data structure of the hash organization. */
+struct mlx5_flow_tbl_data_entry {
+ struct mlx5_hlist_entry entry;
+ /**< hash list entry, 64-bits key inside. */
+ struct mlx5_flow_tbl_resource tbl;
+ /**< flow table resource. */
+ LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
+ /**< matchers' header associated with the flow table. */
+ struct mlx5_flow_dv_jump_tbl_resource jump;
+ /**< jump resource, at most one for each table created. */
+};
+
/*
* Max number of actions per DV flow.
* See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
struct mlx5_flow_meter *fm,
const struct rte_flow_attr *attr);
+int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
+ struct rte_mtr_error *error);
#endif /* RTE_PMD_MLX5_FLOW_H_ */
git.droids-corp.org / dpdk.git / blobdiff