net/mlx5: fix dirty array of actions
[dpdk.git] / drivers / net / mlx5 / mlx5_flow_dv.c
index d51d17d..3daabd3 100644 (file)
@@ -385,10 +385,12 @@ flow_dv_convert_modify_action(struct rte_flow_item *item,
                         off_b - __builtin_clz(mask);
                MLX5_ASSERT(size_b);
                size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
-               actions[i].action_type = type;
-               actions[i].field = field->id;
-               actions[i].offset = off_b;
-               actions[i].length = size_b;
+               actions[i] = (struct mlx5_modification_cmd) {
+                       .action_type = type,
+                       .field = field->id,
+                       .offset = off_b,
+                       .length = size_b,
+               };
                /* Convert entire record to expected big-endian format. */
                actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
                if (type == MLX5_MODIFICATION_TYPE_COPY) {
@@ -578,10 +580,12 @@ flow_dv_convert_action_modify_vlan_vid
                return rte_flow_error_set(error, EINVAL,
                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
                         "too many items to modify");
-       actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
-       actions[i].field = field->id;
-       actions[i].length = field->size;
-       actions[i].offset = field->offset;
+       actions[i] = (struct mlx5_modification_cmd) {
+               .action_type = MLX5_MODIFICATION_TYPE_SET,
+               .field = field->id,
+               .length = field->size,
+               .offset = field->offset,
+       };
        actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
        actions[i].data1 = conf->vlan_vid;
        actions[i].data1 = actions[i].data1 << 16;
@@ -913,8 +917,10 @@ flow_dv_convert_action_set_reg
                                          "too many items to modify");
        MLX5_ASSERT(conf->id != REG_NONE);
        MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
-       actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
-       actions[i].field = reg_to_field[conf->id];
+       actions[i] = (struct mlx5_modification_cmd) {
+               .action_type = MLX5_MODIFICATION_TYPE_SET,
+               .field = reg_to_field[conf->id],
+       };
        actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
        actions[i].data1 = rte_cpu_to_be_32(conf->data);
        ++i;
@@ -5778,6 +5784,76 @@ flow_dv_translate_item_vxlan(void *matcher, void *key,
                vni_v[i] = vni_m[i] & vxlan_v->vni[i];
 }
 
+/**
+ * Add VXLAN-GPE item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+
+static void
+flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
+                                const struct rte_flow_item *item, int inner)
+{
+       const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
+       const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
+       void *headers_m;
+       void *headers_v;
+       void *misc_m =
+               MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
+       void *misc_v =
+               MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
+       char *vni_m;
+       char *vni_v;
+       uint16_t dport;
+       int size;
+       int i;
+       uint8_t flags_m = 0xff;
+       uint8_t flags_v = 0xc;
+
+       if (inner) {
+               headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
+                                        inner_headers);
+               headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
+       } else {
+               headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
+                                        outer_headers);
+               headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
+       }
+       dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
+               MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
+       if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
+               MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
+               MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
+       }
+       if (!vxlan_v)
+               return;
+       if (!vxlan_m)
+               vxlan_m = &rte_flow_item_vxlan_gpe_mask;
+       size = sizeof(vxlan_m->vni);
+       vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
+       vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
+       memcpy(vni_m, vxlan_m->vni, size);
+       for (i = 0; i < size; ++i)
+               vni_v[i] = vni_m[i] & vxlan_v->vni[i];
+       if (vxlan_m->flags) {
+               flags_m = vxlan_m->flags;
+               flags_v = vxlan_v->flags;
+       }
+       MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
+       MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
+       MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
+                vxlan_m->protocol);
+       MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
+                vxlan_v->protocol);
+}
+
 /**
  * Add Geneve item to matcher and to the value.
  *
@@ -7559,8 +7635,9 @@ cnt_err:
                        last_item = MLX5_FLOW_LAYER_VXLAN;
                        break;
                case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
-                       flow_dv_translate_item_vxlan(match_mask, match_value,
-                                                    items, tunnel);
+                       flow_dv_translate_item_vxlan_gpe(match_mask,
+                                                        match_value, items,
+                                                        tunnel);
                        last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
                        break;
                case RTE_FLOW_ITEM_TYPE_GENEVE: