net/mlx5: use flow to enable promiscuous mode

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 89e60ea..ffba64e 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -134,15 +134,46 @@ struct mlx5_rxq_data {
        uint8_t cq_arm_sn; /* CQ arm seq number. */
 } __rte_cache_aligned;
 
-/* RX queue control descriptor. */
-struct mlx5_rxq_ctrl {
-       struct priv *priv; /* Back pointer to private data. */
+/* Verbs Rx queue elements. */
+struct mlx5_rxq_ibv {
+       LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
+       rte_atomic32_t refcnt; /* Reference counter. */
+       struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
        struct ibv_cq *cq; /* Completion Queue. */
        struct ibv_wq *wq; /* Work Queue. */
-       struct mlx5_mr *mr; /* Memory Region (for mp). */
        struct ibv_comp_channel *channel;
-       unsigned int socket; /* CPU socket ID for allocations. */
+       struct mlx5_mr *mr; /* Memory Region (for mp). */
+};
+
+/* RX queue control descriptor. */
+struct mlx5_rxq_ctrl {
+       LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
+       rte_atomic32_t refcnt; /* Reference counter. */
+       struct priv *priv; /* Back pointer to private data. */
+       struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
        struct mlx5_rxq_data rxq; /* Data path structure. */
+       unsigned int socket; /* CPU socket ID for allocations. */
+       unsigned int irq:1; /* Whether IRQ is enabled. */
+};
+
+/* Indirection table. */
+struct mlx5_ind_table_ibv {
+       LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
+       rte_atomic32_t refcnt; /* Reference counter. */
+       struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
+       uint16_t queues_n; /**< Number of queues in the list. */
+       uint16_t queues[]; /**< Queue list. */
+};
+
+/* Hash Rx queue. */
+struct mlx5_hrxq {
+       LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
+       rte_atomic32_t refcnt; /* Reference counter. */
+       struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
+       struct ibv_qp *qp; /* Verbs queue pair. */
+       uint64_t hash_fields; /* Verbs Hash fields. */
+       uint8_t rss_key_len; /* Hash key length in bytes. */
+       uint8_t rss_key[]; /* Hash key. */
 };
 
 /* Hash RX queue types. */
@@ -206,7 +237,6 @@ struct special_flow_init {
 };
 
 enum hash_rxq_flow_type {
-       HASH_RXQ_FLOW_TYPE_PROMISC,
        HASH_RXQ_FLOW_TYPE_ALLMULTI,
        HASH_RXQ_FLOW_TYPE_BROADCAST,
        HASH_RXQ_FLOW_TYPE_IPV6MULTI,
@@ -218,8 +248,6 @@ static inline const char *
 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
 {
        switch (flow_type) {
-       case HASH_RXQ_FLOW_TYPE_PROMISC:
-               return "promiscuous";
        case HASH_RXQ_FLOW_TYPE_ALLMULTI:
                return "allmulticast";
        case HASH_RXQ_FLOW_TYPE_BROADCAST:
@@ -278,12 +306,23 @@ struct mlx5_txq_data {
        struct mlx5_txq_stats stats; /* TX queue counters. */
 } __rte_cache_aligned;
 
+/* Verbs Rx queue elements. */
+struct mlx5_txq_ibv {
+       LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
+       rte_atomic32_t refcnt; /* Reference counter. */
+       struct ibv_cq *cq; /* Completion Queue. */
+       struct ibv_qp *qp; /* Queue Pair. */
+};
+
 /* TX queue control descriptor. */
 struct mlx5_txq_ctrl {
+       LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
+       rte_atomic32_t refcnt; /* Reference counter. */
        struct priv *priv; /* Back pointer to private data. */
-       struct ibv_cq *cq; /* Completion Queue. */
-       struct ibv_qp *qp; /* Queue Pair. */
        unsigned int socket; /* CPU socket ID for allocations. */
+       unsigned int max_inline_data; /* Max inline data. */
+       unsigned int max_tso_header; /* Max TSO header size. */
+       struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
        struct mlx5_txq_data txq; /* Data path structure. */
        off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
 };
@@ -310,16 +349,53 @@ int priv_rx_intr_vec_enable(struct priv *priv);
 void priv_rx_intr_vec_disable(struct priv *priv);
 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_new(struct priv *, uint16_t);
+struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_get(struct priv *, uint16_t);
+int mlx5_priv_rxq_ibv_release(struct priv *, struct mlx5_rxq_ibv *);
+int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *);
+int mlx5_priv_rxq_ibv_verify(struct priv *);
+struct mlx5_rxq_ctrl *mlx5_priv_rxq_new(struct priv *, uint16_t,
+                                       uint16_t, unsigned int,
+                                       struct rte_mempool *);
+struct mlx5_rxq_ctrl *mlx5_priv_rxq_get(struct priv *, uint16_t);
+int mlx5_priv_rxq_release(struct priv *, uint16_t);
+int mlx5_priv_rxq_releasable(struct priv *, uint16_t);
+int mlx5_priv_rxq_verify(struct priv *);
+int rxq_alloc_elts(struct mlx5_rxq_ctrl *);
+struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_new(struct priv *,
+                                                      uint16_t [],
+                                                      uint16_t);
+struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_get(struct priv *,
+                                                      uint16_t [],
+                                                      uint16_t);
+int mlx5_priv_ind_table_ibv_release(struct priv *, struct mlx5_ind_table_ibv *);
+int mlx5_priv_ind_table_ibv_verify(struct priv *);
+struct mlx5_hrxq *mlx5_priv_hrxq_new(struct priv *, uint8_t *, uint8_t,
+                                    uint64_t, uint16_t [], uint16_t);
+struct mlx5_hrxq *mlx5_priv_hrxq_get(struct priv *, uint8_t *, uint8_t,
+                                    uint64_t, uint16_t [], uint16_t);
+int mlx5_priv_hrxq_release(struct priv *, struct mlx5_hrxq *);
+int mlx5_priv_hrxq_ibv_verify(struct priv *);
 
 /* mlx5_txq.c */
 
-void mlx5_txq_cleanup(struct mlx5_txq_ctrl *);
-int mlx5_txq_ctrl_setup(struct rte_eth_dev *, struct mlx5_txq_ctrl *, uint16_t,
-                       unsigned int, const struct rte_eth_txconf *);
 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
                        const struct rte_eth_txconf *);
 void mlx5_tx_queue_release(void *);
 int priv_tx_uar_remap(struct priv *priv, int fd);
+struct mlx5_txq_ibv *mlx5_priv_txq_ibv_new(struct priv *, uint16_t);
+struct mlx5_txq_ibv *mlx5_priv_txq_ibv_get(struct priv *, uint16_t);
+int mlx5_priv_txq_ibv_release(struct priv *, struct mlx5_txq_ibv *);
+int mlx5_priv_txq_ibv_releasable(struct priv *, struct mlx5_txq_ibv *);
+int mlx5_priv_txq_ibv_verify(struct priv *);
+struct mlx5_txq_ctrl *mlx5_priv_txq_new(struct priv *, uint16_t,
+                                       uint16_t, unsigned int,
+                                       const struct rte_eth_txconf *);
+struct mlx5_txq_ctrl *mlx5_priv_txq_get(struct priv *, uint16_t);
+int mlx5_priv_txq_release(struct priv *, uint16_t);
+int mlx5_priv_txq_releasable(struct priv *, uint16_t);
+int mlx5_priv_txq_verify(struct priv *);
+void txq_alloc_elts(struct mlx5_txq_ctrl *);
 
 /* mlx5_rxtx.c */
 
@@ -347,8 +423,9 @@ uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
 
 /* mlx5_mr.c */
 
-struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
-void mlx5_txq_mp2mr_iter(struct rte_mempool *, void *);
+void mlx5_mp2mr_iter(struct rte_mempool *, void *);
+struct mlx5_mr *priv_txq_mp2mr_reg(struct priv *priv, struct mlx5_txq_data *,
+                                  struct rte_mempool *, unsigned int);
 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
                                   unsigned int);