unsigned int i;
int ret = 0;
enum mlx5_rxq_obj_type obj_type = MLX5_RXQ_OBJ_TYPE_IBV;
+ struct mlx5_rxq_data *rxq = NULL;
for (i = 0; i < priv->rxqs_n; ++i) {
- if ((*priv->rxqs)[i]->lro) {
+ rxq = (*priv->rxqs)[i];
+
+ if (rxq && rxq->lro) {
obj_type = MLX5_RXQ_OBJ_TYPE_DEVX_RQ;
break;
}
}
mlx5_txq_release(dev, i);
}
- if (priv->config.dv_esw_en && !priv->config.vf && !priv->representor)
- if (!mlx5_flow_create_esw_table_zero_flow(dev))
- goto error;
+ if (priv->config.dv_esw_en && !priv->config.vf) {
+ if (mlx5_flow_create_esw_table_zero_flow(dev))
+ priv->fdb_def_rule = 1;
+ else
+ DRV_LOG(INFO, "port %u FDB default rule cannot be"
+ " configured - only Eswitch group 0 flows are"
+ " supported.", dev->data->port_id);
+ }
if (priv->isolated)
return 0;
if (dev->data->promiscuous) {