net/mlx5: update Tx error handling routine

[dpdk.git] / drivers / net / mlx5 / mlx5_txq.c

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index a0d6164..78ec361 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -62,7 +62,7 @@ txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
  * @param txq_ctrl
  *   Pointer to TX queue structure.
  */
-static void
+void
 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
 {
        const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
@@ -127,7 +127,8 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
                        offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
                if (config->tso)
                        offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
-                                    DEV_TX_OFFLOAD_GRE_TNL_TSO);
+                                    DEV_TX_OFFLOAD_GRE_TNL_TSO |
+                                    DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
        }
        return offloads;
 }
@@ -271,7 +272,6 @@ mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
        DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
                dev->data->port_id, idx);
        (*priv->txqs)[idx] = &txq_ctrl->txq;
-       txq_ctrl->type = MLX5_TXQ_TYPE_HAIRPIN;
        return 0;
 }
 
@@ -313,8 +313,10 @@ mlx5_tx_queue_release(void *dpdk_txq)
 static void
 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
 {
-       unsigned int cmd;
+       struct mlx5_priv *priv = txq_ctrl->priv;
+       off_t cmd;
 
+       txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
        txq_ctrl->txq.db_nc = 0;
        /* Check the doorbell register mapping type. */
        cmd = txq_ctrl->uar_mmap_offset / page_size;
@@ -955,7 +957,7 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
                     (unsigned int)config->txq_inline_mpw;
        inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
                     0 : (unsigned int)config->txq_inline_min;
-       if (config->mps != MLX5_MPW_ENHANCED)
+       if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
                inlen_empw = 0;
        /*
         * If there is requested minimal amount of data to inline
@@ -1210,7 +1212,8 @@ txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
        assert(txq_ctrl->max_inline_data <= max_inline);
        assert(txq_ctrl->txq.inlen_mode <= max_inline);
        assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
-       assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw);
+       assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
+              !txq_ctrl->txq.inlen_empw);
        return 0;
 error:
        rte_errno = ENOMEM;