offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
if (config->tso)
offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
- DEV_TX_OFFLOAD_GRE_TNL_TSO);
+ DEV_TX_OFFLOAD_GRE_TNL_TSO |
+ DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
}
return offloads;
}
(unsigned int)config->txq_inline_mpw;
inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
0 : (unsigned int)config->txq_inline_min;
- if (config->mps != MLX5_MPW_ENHANCED)
+ if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
inlen_empw = 0;
/*
* If there is requested minimal amount of data to inline
assert(txq_ctrl->max_inline_data <= max_inline);
assert(txq_ctrl->txq.inlen_mode <= max_inline);
assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
- assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw);
+ assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
+ !txq_ctrl->txq.inlen_empw);
return 0;
error:
rte_errno = ENOMEM;