net/octeontx2: support reduced set of packet types

[dpdk.git] / drivers / net / octeontx2 / otx2_ethdev.c

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index dfa8cd2..ddab3aa 100644 (file)
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -86,6 +86,7 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
        dev->cints = rsp->cints;
        dev->qints = rsp->qints;
        dev->npc_flow.channel = dev->rx_chan_base;
+       dev->ptp_en = rsp->hw_rx_tstamp_en;
 
        return 0;
 }
@@ -144,7 +145,7 @@ otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
 {
        struct otx2_mbox *mbox = dev->mbox;
 
-       if (otx2_dev_is_vf(dev))
+       if (otx2_dev_is_vf_or_sdp(dev))
                return 0;
 
        otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
@@ -157,7 +158,7 @@ otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
 {
        struct otx2_mbox *mbox = dev->mbox;
 
-       if (otx2_dev_is_vf(dev))
+       if (otx2_dev_is_vf_or_sdp(dev))
                return 0;
 
        otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
@@ -190,7 +191,7 @@ nix_cgx_start_link_event(struct otx2_eth_dev *dev)
 {
        struct otx2_mbox *mbox = dev->mbox;
 
-       if (otx2_dev_is_vf(dev))
+       if (otx2_dev_is_vf_or_sdp(dev))
                return 0;
 
        otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
@@ -203,7 +204,7 @@ cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
 {
        struct otx2_mbox *mbox = dev->mbox;
 
-       if (otx2_dev_is_vf(dev))
+       if (otx2_dev_is_vf_or_sdp(dev))
                return 0;
 
        if (en)
@@ -219,7 +220,7 @@ nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
 {
        struct otx2_mbox *mbox = dev->mbox;
 
-       if (otx2_dev_is_vf(dev))
+       if (otx2_dev_is_vf_or_sdp(dev))
                return 0;
 
        otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
@@ -599,7 +600,8 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
        struct rte_eth_rxmode *rxmode = &conf->rxmode;
        uint16_t flags = 0;
 
-       if (rxmode->mq_mode == ETH_MQ_RX_RSS)
+       if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
+                       (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
                flags |= NIX_RX_OFFLOAD_RSS_F;
 
        if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
@@ -1700,13 +1702,13 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
        rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
        if (rc) {
                otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
-               goto q_irq_fini;
+               goto cq_fini;
        }
 
        rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
        if (rc) {
                otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
-               goto q_irq_fini;
+               goto cq_fini;
        }
 
        rc = otx2_nix_mc_addr_list_install(eth_dev);
@@ -1899,7 +1901,11 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
        struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
        int rc, i;
 
-       if (eth_dev->data->nb_rx_queues != 0) {
+       /* MTU recalculate should be avoided here if PTP is enabled by PF, as
+        * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
+        * call below.
+        */
+       if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
                rc = otx2_nix_recalc_mtu(eth_dev);
                if (rc)
                        return rc;
@@ -1935,6 +1941,12 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
        else
                otx2_nix_timesync_disable(eth_dev);
 
+       /* Update VF about data off shifted by 8 bytes if PTP already
+        * enabled in PF owning this VF
+        */
+       if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
+               otx2_nix_ptp_enable_vf(eth_dev);
+
        rc = npc_rx_enable(dev);
        if (rc) {
                otx2_err("Failed to enable NPC rx %d", rc);
@@ -1983,6 +1995,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
        .dev_set_link_up          = otx2_nix_dev_set_link_up,
        .dev_set_link_down        = otx2_nix_dev_set_link_down,
        .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
+       .dev_ptypes_set           = otx2_nix_ptypes_set,
        .dev_reset                = otx2_nix_dev_reset,
        .stats_get                = otx2_nix_dev_stats_get,
        .stats_reset              = otx2_nix_dev_stats_reset,
@@ -2008,6 +2021,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
        .xstats_get_names_by_id   = otx2_nix_xstats_get_names_by_id,
        .rxq_info_get             = otx2_nix_rxq_info_get,
        .txq_info_get             = otx2_nix_txq_info_get,
+       .rx_burst_mode_get        = otx2_rx_burst_mode_get,
+       .tx_burst_mode_get        = otx2_tx_burst_mode_get,
        .rx_queue_count           = otx2_nix_rx_queue_count,
        .rx_descriptor_done       = otx2_nix_rx_descriptor_done,
        .rx_descriptor_status     = otx2_nix_rx_descriptor_status,
@@ -2086,6 +2101,15 @@ otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
        return otx2_mbox_process(mbox);
 }
 
+static bool
+otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
+{
+       if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
+           pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
+               return true;
+       return false;
+}
+
 static int
 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
 {
@@ -2129,6 +2153,10 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
                        goto error;
                }
        }
+       if (otx2_eth_dev_is_sdp(pci_dev))
+               dev->sdp_link = true;
+       else
+               dev->sdp_link = false;
        /* Device generic callbacks */
        dev->ops = &otx2_dev_ops;
        dev->eth_dev = eth_dev;
@@ -2416,6 +2444,14 @@ static const struct rte_pci_id pci_nix_map[] = {
                RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
                               PCI_DEVID_OCTEONTX2_RVU_AF_VF)
        },
+       {
+               RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+                              PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
+       },
+       {
+               RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+                              PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
+       },
        {
                .vendor_id = 0,
        },