net/octeontx2: add Rx queue setup and release

[dpdk.git] / drivers / net / octeontx2 / otx2_ethdev.h

diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index 7d53a66..a093933 100644 (file)
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -10,6 +10,9 @@
 #include <rte_common.h>
 #include <rte_ethdev.h>
 #include <rte_kvargs.h>
+#include <rte_mbuf.h>
+#include <rte_mempool.h>
+#include <rte_string_fns.h>
 
 #include "otx2_common.h"
 #include "otx2_dev.h"
@@ -59,6 +62,7 @@
 
 #define NIX_MAX_SQB                    512
 #define NIX_MIN_SQB                    32
+#define NIX_RSS_RETA_SIZE_MAX          256
 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
 #define NIX_RSS_GRPS                   8
 #define NIX_HASH_KEY_SIZE              48 /* 352 Bits */
@@ -67,6 +71,7 @@
 #define NIX_RX_MIN_DESC_ALIGN          16
 #define NIX_RX_NB_SEG_MAX              6
 #define NIX_CQ_ENTRY_SZ                        128
+#define NIX_CQ_ALIGN                   512
 
 /* If PTP is enabled additional SEND MEM DESC is required which
  * takes 2 words, hence max 7 iova address are possible
@@ -112,14 +117,45 @@
        DEV_RX_OFFLOAD_QINQ_STRIP | \
        DEV_RX_OFFLOAD_TIMESTAMP)
 
+#define NIX_DEFAULT_RSS_CTX_GROUP  0
+#define NIX_DEFAULT_RSS_MCAM_IDX  -1
+
+enum nix_q_size_e {
+       nix_q_size_16,  /* 16 entries */
+       nix_q_size_64,  /* 64 entries */
+       nix_q_size_256,
+       nix_q_size_1K,
+       nix_q_size_4K,
+       nix_q_size_16K,
+       nix_q_size_64K,
+       nix_q_size_256K,
+       nix_q_size_1M,  /* Million entries */
+       nix_q_size_max
+};
+
 struct otx2_qint {
        struct rte_eth_dev *eth_dev;
        uint8_t qintx;
 };
 
 struct otx2_rss_info {
+       uint64_t nix_rss;
+       uint32_t flowkey_cfg;
        uint16_t rss_size;
        uint8_t rss_grps;
+       uint8_t alg_idx; /* Selected algo index */
+       uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
+       uint8_t key[NIX_HASH_KEY_SIZE];
+};
+
+struct otx2_eth_qconf {
+       union {
+               struct rte_eth_txconf tx;
+               struct rte_eth_rxconf rx;
+       } conf;
+       void *mempool;
+       uint32_t socket_id;
+       uint16_t nb_desc;
 };
 
 struct otx2_npc_flow_info {
@@ -168,6 +204,29 @@ struct otx2_eth_dev {
        struct rte_eth_dev *eth_dev;
 } __rte_cache_aligned;
 
+struct otx2_eth_rxq {
+       uint64_t mbuf_initializer;
+       uint64_t data_off;
+       uintptr_t desc;
+       void *lookup_mem;
+       uintptr_t cq_door;
+       uint64_t wdata;
+       int64_t *cq_status;
+       uint32_t head;
+       uint32_t qmask;
+       uint32_t available;
+       uint16_t rq;
+       struct otx2_timesync_info *tstamp;
+       MARKER slow_path_start;
+       uint64_t aura;
+       uint64_t offloads;
+       uint32_t qlen;
+       struct rte_mempool *pool;
+       enum nix_q_size_e qsize;
+       struct rte_eth_dev *eth_dev;
+       struct otx2_eth_qconf qconf;
+} __rte_cache_aligned;
+
 static inline struct otx2_eth_dev *
 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 {
@@ -178,6 +237,13 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
                       struct rte_eth_dev_info *dev_info);
 
+void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
+void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
+void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
+void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
+void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
+uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
+
 /* Link */
 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
@@ -219,6 +285,30 @@ int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
                                    struct rte_eth_xstat_name *xstats_names,
                                    const uint64_t *ids, unsigned int limit);
 
+/* RSS */
+void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
+                         uint8_t *key, uint32_t key_len);
+uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
+                               uint64_t ethdev_rss, uint8_t rss_level);
+int otx2_rss_set_hf(struct otx2_eth_dev *dev,
+                   uint32_t flowkey_cfg, uint8_t *alg_idx,
+                   uint8_t group, int mcam_index);
+int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
+                         uint16_t *ind_tbl);
+int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
+
+int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
+                            struct rte_eth_rss_reta_entry64 *reta_conf,
+                            uint16_t reta_size);
+int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
+                           struct rte_eth_rss_reta_entry64 *reta_conf,
+                           uint16_t reta_size);
+int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
+                            struct rte_eth_rss_conf *rss_conf);
+
+int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
+                              struct rte_eth_rss_conf *rss_conf);
+
 /* CGX */
 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
@@ -226,7 +316,13 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
                          struct rte_ether_addr *addr);
 
 /* Mac address handling */
+int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
+                         struct rte_ether_addr *addr);
 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
+int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
+                         struct rte_ether_addr *addr,
+                         uint32_t index, uint32_t pool);
+void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
 
 /* Devargs */