net/qede/base: update FW to 8.40.25.0

[dpdk.git] / drivers / net / qede / base / ecore.h

diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index b1d8706..925b75c 100644 (file)
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -28,8 +28,8 @@
 #include "mcp_public.h"
 
 #define ECORE_MAJOR_VERSION            8
-#define ECORE_MINOR_VERSION            37
-#define ECORE_REVISION_VERSION         20
+#define ECORE_MINOR_VERSION            40
+#define ECORE_REVISION_VERSION         18
 #define ECORE_ENGINEERING_VERSION      0
 
 #define ECORE_VERSION                                                  \
@@ -467,6 +467,8 @@ struct ecore_wfq_data {
        bool configured;
 };
 
+#define OFLD_GRP_SIZE 4
+
 struct ecore_qm_info {
        struct init_qm_pq_params    *qm_pq_params;
        struct init_qm_vport_params *qm_vport_params;
@@ -513,6 +515,8 @@ struct ecore_fw_data {
        const u8 *modes_tree_buf;
        union init_op *init_ops;
        const u32 *arr_data;
+       const u32 *fw_overlays;
+       u32 fw_overlays_len;
        u32 init_ops_size;
 };
 
@@ -592,6 +596,7 @@ struct ecore_hwfn {
 
        u8                              num_funcs_on_engine;
        u8                              enabled_func_idx;
+       u8                              num_funcs_on_port;
 
        /* BAR access */
        void OSAL_IOMEM                 *regview;
@@ -745,7 +750,6 @@ struct ecore_dev {
 #endif
 #define ECORE_IS_AH(dev)       ((dev)->type == ECORE_DEV_TYPE_AH)
 #define ECORE_IS_K2(dev)       ECORE_IS_AH(dev)
-#define ECORE_IS_E4(dev)       (ECORE_IS_BB(dev) || ECORE_IS_AH(dev))
 
        u16 vendor_id;
        u16 device_id;
@@ -893,6 +897,7 @@ struct ecore_dev {
 
 #ifndef ASIC_ONLY
        bool                            b_is_emul_full;
+       bool                            b_is_emul_mac;
 #endif
        /* LLH info */
        u8                              ppfid_bitmap;
@@ -911,16 +916,52 @@ struct ecore_dev {
        u8                              engine_for_debug;
 };
 
-#define NUM_OF_VFS(dev)                (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
-                                                 : MAX_NUM_VFS_K2)
-#define NUM_OF_L2_QUEUES(dev)  (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
-                                                 : MAX_NUM_L2_QUEUES_K2)
-#define NUM_OF_PORTS(dev)      (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
-                                                 : MAX_NUM_PORTS_K2)
-#define NUM_OF_SBS(dev)                (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
-                                                 : MAX_SB_PER_PATH_K2)
-#define NUM_OF_ENG_PFS(dev)    (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
-                                                 : MAX_NUM_PFS_K2)
+enum ecore_hsi_def_type {
+       ECORE_HSI_DEF_MAX_NUM_VFS,
+       ECORE_HSI_DEF_MAX_NUM_L2_QUEUES,
+       ECORE_HSI_DEF_MAX_NUM_PORTS,
+       ECORE_HSI_DEF_MAX_SB_PER_PATH,
+       ECORE_HSI_DEF_MAX_NUM_PFS,
+       ECORE_HSI_DEF_MAX_NUM_VPORTS,
+       ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE,
+       ECORE_HSI_DEF_MAX_QM_TX_QUEUES,
+       ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS,
+       ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
+       ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS,
+       ECORE_HSI_DEF_MAX_PBF_CMD_LINES,
+       ECORE_HSI_DEF_MAX_BTB_BLOCKS,
+       ECORE_NUM_HSI_DEFS
+};
+
+u32 ecore_get_hsi_def_val(struct ecore_dev *p_dev,
+                         enum ecore_hsi_def_type type);
+
+#define NUM_OF_VFS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VFS)
+#define NUM_OF_L2_QUEUES(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_L2_QUEUES)
+#define NUM_OF_PORTS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PORTS)
+#define NUM_OF_SBS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_SB_PER_PATH)
+#define NUM_OF_ENG_PFS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_PFS)
+#define NUM_OF_VPORTS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_NUM_VPORTS)
+#define NUM_OF_RSS_ENGINES(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_ETH_RSS_ENGINE)
+#define NUM_OF_QM_TX_QUEUES(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_TX_QUEUES)
+#define NUM_OF_PXP_ILT_RECORDS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_PXP_ILT_RECORDS)
+#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
+#define NUM_OF_QM_GLOBAL_RLS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_QM_GLOBAL_RLS)
+#define NUM_OF_PBF_CMD_LINES(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_PBF_CMD_LINES)
+#define NUM_OF_BTB_BLOCKS(dev) \
+       ecore_get_hsi_def_val(dev, ECORE_HSI_DEF_MAX_BTB_BLOCKS)
 
 #define CRC8_TABLE_SIZE 256
 
@@ -948,7 +989,6 @@ static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
 }
 
 #define PKT_LB_TC 9
-#define MAX_NUM_VOQS_E4 20
 
 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
@@ -1023,4 +1063,9 @@ enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
 
+#define TSTORM_QZONE_START     PXP_VF_BAR0_START_SDM_ZONE_A
+
+#define MSTORM_QZONE_START(dev) \
+       (TSTORM_QZONE_START + (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
+
 #endif /* __ECORE_H */