net/qede: change copyright info to Cavium

[dpdk.git] / drivers / net / qede / base / ecore_int.c

diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c
index d86f56e..7272f05 100644 (file)
--- a/drivers/net/qede/base/ecore_int.c
+++ b/drivers/net/qede/base/ecore_int.c
@@ -1,15 +1,16 @@
 /*
- * Copyright (c) 2016 QLogic Corporation.
+ * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
+ * www.cavium.com
  *
  * See LICENSE.qede_pmd for copyright and licensing details.
  */
 
+#include <rte_string_fns.h>
+
 #include "bcm_osal.h"
 #include "ecore.h"
 #include "ecore_spq.h"
-#include "reg_addr.h"
 #include "ecore_gtt_reg_addr.h"
 #include "ecore_init_ops.h"
 #include "ecore_rt_defs.h"
@@ -30,7 +31,7 @@ struct ecore_pi_info {
 struct ecore_sb_sp_info {
        struct ecore_sb_info sb_info;
        /* per protocol index data */
-       struct ecore_pi_info pi_info_arr[PIS_PER_SB];
+       struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
 };
 
 enum ecore_attention_type {
@@ -286,9 +287,11 @@ out:
 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 
 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
-                                                  struct ecore_ptt *p_ptt)
+                                                  struct ecore_ptt *p_ptt,
+                                                  bool is_hw_init)
 {
        u32 tmp;
+       char str[512] = {0};
 
        tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
        if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
@@ -300,9 +303,8 @@ enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
                                   PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
                details = ecore_rd(p_hwfn, p_ptt,
                                   PGLUE_B_REG_TX_ERR_WR_DETAILS);
-
-               DP_NOTICE(p_hwfn, false,
-                         "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
+               OSAL_SNPRINTF(str, 512,
+                        "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
                          addr_hi, addr_lo, details,
                          (u8)((details &
                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
@@ -319,6 +321,10 @@ enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
                                1 : 0),
                          (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
                                1 : 0));
+               if (is_hw_init)
+                       DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "%s", str);
+               else
+                       DP_NOTICE(p_hwfn, false, "%s", str);
        }
 
        tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
@@ -394,7 +400,7 @@ enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 
 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 {
-       return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);
+       return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false);
 }
 
 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
@@ -1105,9 +1111,9 @@ static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
                                                              p_aeu->bit_name,
                                                              num);
                                        else
-                                               OSAL_STRNCPY(bit_name,
-                                                            p_aeu->bit_name,
-                                                            30);
+                                               strlcpy(bit_name,
+                                                       p_aeu->bit_name,
+                                                       sizeof(bit_name));
 
                                        /* We now need to pass bitmask in its
                                         * correct position.
@@ -1407,8 +1413,7 @@ static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
        /* SB struct */
        p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
        if (!p_sb) {
-               DP_NOTICE(p_dev, true,
-                         "Failed to allocate `struct ecore_sb_attn_info'\n");
+               DP_NOTICE(p_dev, false, "Failed to allocate `struct ecore_sb_attn_info'\n");
                return ECORE_NOMEM;
        }
 
@@ -1416,8 +1421,7 @@ static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
        p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
                                         SB_ATTN_ALIGNED_SIZE(p_hwfn));
        if (!p_virt) {
-               DP_NOTICE(p_dev, true,
-                         "Failed to allocate status block (attentions)\n");
+               DP_NOTICE(p_dev, false, "Failed to allocate status block (attentions)\n");
                OSAL_FREE(p_dev, p_sb);
                return ECORE_NOMEM;
        }
@@ -1492,7 +1496,7 @@ static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
        if (IS_VF(p_hwfn->p_dev))
                return;/* @@@TBD MichalK- VF CAU... */
 
-       sb_offset = igu_sb_id * PIS_PER_SB;
+       sb_offset = igu_sb_id * PIS_PER_SB_E4;
        OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
 
        SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
@@ -1796,8 +1800,7 @@ static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
            OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
                       sizeof(*p_sb));
        if (!p_sb) {
-               DP_NOTICE(p_hwfn, true,
-                         "Failed to allocate `struct ecore_sb_info'\n");
+               DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_sb_info'\n");
                return ECORE_NOMEM;
        }
 
@@ -1805,7 +1808,7 @@ static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
        p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
                                         &p_phys, SB_ALIGNED_SIZE(p_hwfn));
        if (!p_virt) {
-               DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
+               DP_NOTICE(p_hwfn, false, "Failed to allocate status block\n");
                OSAL_FREE(p_hwfn->p_dev, p_sb);
                return ECORE_NOMEM;
        }
@@ -1926,15 +1929,6 @@ ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
                          enum ecore_int_mode int_mode)
 {
        enum _ecore_status_t rc = ECORE_SUCCESS;
-       u32 tmp;
-
-       /* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
-        * attentions. Since we're waiting for BRCM answer regarding this
-        * attention, in the meanwhile we simply mask it.
-        */
-       tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
-       tmp &= ~0x800;
-       ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
 
        ecore_int_igu_enable_attn(p_hwfn, p_ptt);
 
@@ -2677,10 +2671,11 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
        p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
                                    IGU_REG_CONSUMER_MEM + sbid * 4);
 
-       for (i = 0; i < PIS_PER_SB; i++)
+       for (i = 0; i < PIS_PER_SB_E4; i++)
                p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
                                              CAU_REG_PI_MEMORY +
-                                             sbid * 4 * PIS_PER_SB +  i * 4);
+                                             sbid * 4 * PIS_PER_SB_E4 +
+                                             i * 4);
 
        return ECORE_SUCCESS;
 }