net/qede: support LRO/TSO offloads

[dpdk.git] / drivers / net / qede / qede_rxtx.h

diff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h
index 2a8645a..c27632e 100644 (file)
--- a/drivers/net/qede/qede_rxtx.h
+++ b/drivers/net/qede/qede_rxtx.h
@@ -41,10 +41,6 @@
                (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
                (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
                (bd)->nbytes = rte_cpu_to_le_16(len); \
-               /* FW 8.10.x specific change */  \
-               (bd)->data.bitfields = ((len) & \
-                                        ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) \
-                                       << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; \
        } while (0)
 
 #define CQE_HAS_VLAN(flags) \
@@ -55,14 +51,21 @@
        ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
                << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
 
+#define QEDE_MIN_RX_BUFF_SIZE          (1024)
+#define QEDE_VLAN_TAG_SIZE             (4)
+#define QEDE_LLC_SNAP_HDR_LEN          (8)
+
 /* Max supported alignment is 256 (8 shift)
  * minimal alignment shift 6 is optimal for 57xxx HW performance
  */
 #define QEDE_L1_CACHE_SHIFT    6
 #define QEDE_RX_ALIGN_SHIFT    (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
 #define QEDE_FW_RX_ALIGN_END   (1UL << QEDE_RX_ALIGN_SHIFT)
-
-#define QEDE_ETH_OVERHEAD       (ETHER_HDR_LEN + 8 + 8 + QEDE_FW_RX_ALIGN_END)
+#define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
+                                       ~(QEDE_FW_RX_ALIGN_END - 1))
+/* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
+#define QEDE_ETH_OVERHEAD      ((ETHER_HDR_LEN) + ((2 * QEDE_VLAN_TAG_SIZE)) \
+                               + (QEDE_LLC_SNAP_HDR_LEN))
 
 #define QEDE_RSS_OFFLOAD_ALL    (ETH_RSS_IPV4                  |\
                                 ETH_RSS_NONFRAG_IPV4_TCP       |\
@@ -123,6 +126,19 @@
 
 #define QEDE_PKT_TYPE_TUNN_MAX_TYPE                    0x20 /* 2^5 */
 
+#define QEDE_TX_CSUM_OFFLOAD_MASK (PKT_TX_IP_CKSUM              | \
+                                  PKT_TX_TCP_CKSUM             | \
+                                  PKT_TX_UDP_CKSUM             | \
+                                  PKT_TX_OUTER_IP_CKSUM        | \
+                                  PKT_TX_TCP_SEG)
+
+#define QEDE_TX_OFFLOAD_MASK (QEDE_TX_CSUM_OFFLOAD_MASK | \
+                             PKT_TX_QINQ_PKT           | \
+                             PKT_TX_VLAN_PKT)
+
+#define QEDE_TX_OFFLOAD_NOTSUP_MASK \
+       (PKT_TX_OFFLOAD_MASK ^ QEDE_TX_OFFLOAD_MASK)
+
 /*
  * RX BD descriptor ring
  */
@@ -132,6 +148,19 @@ struct qede_rx_entry {
        /* allows expansion .. */
 };
 
+/* TPA related structures */
+enum qede_agg_state {
+       QEDE_AGG_STATE_NONE  = 0,
+       QEDE_AGG_STATE_START = 1,
+       QEDE_AGG_STATE_ERROR = 2
+};
+
+struct qede_agg_info {
+       struct rte_mbuf *mbuf;
+       uint16_t start_cqe_bd_len;
+       uint8_t state; /* for sanity check */
+};
+
 /*
  * Structure associated with each RX queue.
  */
@@ -152,7 +181,9 @@ struct qede_rx_queue {
        uint64_t rx_segs;
        uint64_t rx_hw_errors;
        uint64_t rx_alloc_errors;
+       struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
        struct qede_dev *qdev;
+       void *handle;
 };
 
 /*
@@ -184,6 +215,7 @@ struct qede_tx_queue {
        uint64_t xmit_pkts;
        bool is_legacy;
        struct qede_dev *qdev;
+       void *handle;
 };
 
 struct qede_fastpath {
@@ -227,6 +259,9 @@ void qede_free_mem_load(struct rte_eth_dev *eth_dev);
 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
                        uint16_t nb_pkts);
 
+uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
+                            uint16_t nb_pkts);
+
 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
                        uint16_t nb_pkts);