net/sfc/base: import SFN7xxx family support

[dpdk.git] / drivers / net / sfc / base / efx_impl.h

diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index c6ec808..10ab36b 100644 (file)
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -41,6 +41,18 @@
 #endif
 
 
+#if EFSYS_OPT_SIENA
+#include "siena_impl.h"
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+#include "hunt_impl.h"
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
+#include "ef10_impl.h"
+#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -274,9 +286,73 @@ typedef struct efx_nic_ops_s {
 
 #if EFSYS_OPT_FILTER
 
+#if EFSYS_OPT_SIENA
+
+typedef struct siena_filter_spec_s {
+       uint8_t         sfs_type;
+       uint32_t        sfs_flags;
+       uint32_t        sfs_dmaq_id;
+       uint32_t        sfs_dword[3];
+} siena_filter_spec_t;
+
+typedef enum siena_filter_type_e {
+       EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
+       EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
+       EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
+       EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
+       EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
+       EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
+
+       EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
+       EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
+       EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
+       EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
+       EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
+       EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
+
+       EFX_SIENA_FILTER_NTYPES
+} siena_filter_type_t;
+
+typedef enum siena_filter_tbl_id_e {
+       EFX_SIENA_FILTER_TBL_RX_IP = 0,
+       EFX_SIENA_FILTER_TBL_RX_MAC,
+       EFX_SIENA_FILTER_TBL_TX_IP,
+       EFX_SIENA_FILTER_TBL_TX_MAC,
+       EFX_SIENA_FILTER_NTBLS
+} siena_filter_tbl_id_t;
+
+typedef struct siena_filter_tbl_s {
+       int                     sft_size;       /* number of entries */
+       int                     sft_used;       /* active count */
+       uint32_t                *sft_bitmap;    /* active bitmap */
+       siena_filter_spec_t     *sft_spec;      /* array of saved specs */
+} siena_filter_tbl_t;
+
+typedef struct siena_filter_s {
+       siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
+       unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
+} siena_filter_t;
+
+#endif /* EFSYS_OPT_SIENA */
+
 typedef struct efx_filter_s {
+#if EFSYS_OPT_SIENA
+       siena_filter_t          *ef_siena_filter;
+#endif /* EFSYS_OPT_SIENA */
+#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+       ef10_filter_table_t     *ef_ef10_filter_table;
+#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 } efx_filter_t;
 
+#if EFSYS_OPT_SIENA
+
+extern                 void
+siena_filter_tbl_clear(
+       __in            efx_nic_t *enp,
+       __in            siena_filter_tbl_id_t tbl);
+
+#endif /* EFSYS_OPT_SIENA */
+
 #endif /* EFSYS_OPT_FILTER */
 
 #if EFSYS_OPT_MCDI
@@ -341,8 +417,31 @@ struct efx_nic_s {
 #endif /* EFSYS_OPT_MCDI */
        uint32_t                en_vport_id;
        union {
+#if EFSYS_OPT_SIENA
+               struct {
+                       int                     enu_unused;
+               } siena;
+#endif /* EFSYS_OPT_SIENA */
                int     enu_unused;
        } en_u;
+#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
+       union en_arch {
+               struct {
+                       int                     ena_vi_base;
+                       int                     ena_vi_count;
+                       int                     ena_vi_shift;
+                       efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
+                       uint32_t                ena_piobuf_count;
+                       uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
+                       uint32_t                ena_pio_write_vi_base;
+                       /* Memory BAR mapping regions */
+                       uint32_t                ena_uc_mem_map_offset;
+                       size_t                  ena_uc_mem_map_size;
+                       uint32_t                ena_wc_mem_map_offset;
+                       size_t                  ena_wc_mem_map_size;
+               } ef10;
+       } en_arch;
+#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 };
 
 
@@ -399,6 +498,13 @@ struct efx_txq_s {
        unsigned int                    et_index;
        unsigned int                    et_mask;
        efsys_mem_t                     *et_esmp;
+#if EFSYS_OPT_HUNTINGTON
+       uint32_t                        et_pio_bufnum;
+       uint32_t                        et_pio_blknum;
+       uint32_t                        et_pio_write_offset;
+       uint32_t                        et_pio_offset;
+       size_t                          et_pio_size;
+#endif
 };
 
 #define        EFX_TXQ_MAGIC   0x05092005