net/sfc: support regioned NIC DMA memory mapping type

[dpdk.git] / drivers / net / sfc / sfc_ef10_essb_rx.c

diff --git a/drivers/net/sfc/sfc_ef10_essb_rx.c b/drivers/net/sfc/sfc_ef10_essb_rx.c
index 63da807..712c207 100644 (file)
--- a/drivers/net/sfc/sfc_ef10_essb_rx.c
+++ b/drivers/net/sfc/sfc_ef10_essb_rx.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright (c) 2017-2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2021 Xilinx, Inc.
+ * Copyright(c) 2017-2019 Solarflare Communications Inc.
  *
  * This software was jointly developed between OKTET Labs (under contract
  * for Solarflare) and Solarflare Communications, Inc.
@@ -12,15 +12,14 @@
 #include <stdbool.h>
 
 #include <rte_byteorder.h>
-#include <rte_mbuf_ptype.h>
 #include <rte_mbuf.h>
 #include <rte_io.h>
 
-#include "efx.h"
 #include "efx_types.h"
-#include "efx_regs.h"
 #include "efx_regs_ef10.h"
+#include "efx.h"
 
+#include "sfc_debug.h"
 #include "sfc_tweak.h"
 #include "sfc_dp_rx.h"
 #include "sfc_kvargs.h"
@@ -48,7 +47,7 @@
  * Each HW Rx descriptor has many Rx buffers. The number of buffers
  * in one HW Rx descriptor is equal to size of contiguous block
  * provided by Rx buffers memory pool. The contiguous block size
- * depends on CONFIG_RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB and rte_mbuf
+ * depends on RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB and rte_mbuf
  * data size specified on the memory pool creation. Typical rte_mbuf
  * data size is about 2k which makes a bit less than 32 buffers in
  * contiguous block with default bucket size equal to 64k.
@@ -126,7 +125,7 @@ sfc_ef10_essb_next_mbuf(const struct sfc_ef10_essb_rxq *rxq,
        struct rte_mbuf *m;
 
        m = (struct rte_mbuf *)((uintptr_t)mbuf + rxq->buf_stride);
-       MBUF_RAW_ALLOC_CHECK(m);
+       __rte_mbuf_raw_sanity_check(m);
        return m;
 }
 
@@ -137,7 +136,7 @@ sfc_ef10_essb_mbuf_by_index(const struct sfc_ef10_essb_rxq *rxq,
        struct rte_mbuf *m;
 
        m = (struct rte_mbuf *)((uintptr_t)mbuf + idx * rxq->buf_stride);
-       MBUF_RAW_ALLOC_CHECK(m);
+       __rte_mbuf_raw_sanity_check(m);
        return m;
 }
 
@@ -221,7 +220,8 @@ sfc_ef10_essb_rx_qrefill(struct sfc_ef10_essb_rxq *rxq)
 
        SFC_ASSERT(rxq->added != added);
        rxq->added = added;
-       sfc_ef10_rx_qpush(rxq->doorbell, added, rxq_ptr_mask);
+       sfc_ef10_rx_qpush(rxq->doorbell, added, rxq_ptr_mask,
+                         &rxq->dp.dpq.dbells);
 }
 
 static bool
@@ -306,6 +306,27 @@ sfc_ef10_essb_rx_process_ev(struct sfc_ef10_essb_rxq *rxq, efx_qword_t rx_ev)
        } while (ready > 0);
 }
 
+/*
+ * Below function relies on the following length and layout of the
+ * Rx prefix.
+ */
+static const efx_rx_prefix_layout_t sfc_ef10_essb_rx_prefix_layout = {
+       .erpl_length    = ES_EZ_ESSB_RX_PREFIX_LEN,
+       .erpl_fields    = {
+#define        SFC_EF10_ESSB_RX_PREFIX_FIELD(_efx, _ef10) \
+       EFX_RX_PREFIX_FIELD(_efx, ES_EZ_ESSB_RX_PREFIX_ ## _ef10, B_FALSE)
+
+               SFC_EF10_ESSB_RX_PREFIX_FIELD(LENGTH, DATA_LEN),
+               SFC_EF10_ESSB_RX_PREFIX_FIELD(USER_MARK, MARK),
+               SFC_EF10_ESSB_RX_PREFIX_FIELD(RSS_HASH_VALID, HASH_VALID),
+               SFC_EF10_ESSB_RX_PREFIX_FIELD(USER_MARK_VALID, MARK_VALID),
+               SFC_EF10_ESSB_RX_PREFIX_FIELD(USER_FLAG, MATCH_FLAG),
+               SFC_EF10_ESSB_RX_PREFIX_FIELD(RSS_HASH, HASH),
+
+#undef SFC_EF10_ESSB_RX_PREFIX_FIELD
+       }
+};
+
 static unsigned int
 sfc_ef10_essb_rx_get_pending(struct sfc_ef10_essb_rxq *rxq,
                             struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
@@ -353,13 +374,13 @@ sfc_ef10_essb_rx_get_pending(struct sfc_ef10_essb_rxq *rxq,
                        rte_pktmbuf_data_len(m) = pkt_len;
 
                        m->ol_flags |=
-                               (PKT_RX_RSS_HASH *
+                               (RTE_MBUF_F_RX_RSS_HASH *
                                 !!EFX_TEST_QWORD_BIT(*qwordp,
                                        ES_EZ_ESSB_RX_PREFIX_HASH_VALID_LBN)) |
-                               (PKT_RX_FDIR_ID *
+                               (RTE_MBUF_F_RX_FDIR_ID *
                                 !!EFX_TEST_QWORD_BIT(*qwordp,
                                        ES_EZ_ESSB_RX_PREFIX_MARK_VALID_LBN)) |
-                               (PKT_RX_FDIR *
+                               (RTE_MBUF_F_RX_FDIR *
                                 !!EFX_TEST_QWORD_BIT(*qwordp,
                                        ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_LBN));
 
@@ -552,6 +573,10 @@ sfc_ef10_essb_rx_qcreate(uint16_t port_id, uint16_t queue_id,
        struct sfc_ef10_essb_rxq *rxq;
        int rc;
 
+       rc = ENOTSUP;
+       if (info->nic_dma_info->nb_regions > 0)
+               goto fail_nic_dma;
+
        rc = rte_mempool_ops_get_info(mp, &mp_info);
        if (rc != 0) {
                /* Positive errno is used in the driver */
@@ -598,6 +623,8 @@ sfc_ef10_essb_rx_qcreate(uint16_t port_id, uint16_t queue_id,
                        ER_DZ_RX_DESC_UPD_REG_OFST +
                        (info->hw_index << info->vi_window_shift);
 
+       sfc_ef10_essb_rx_info(&rxq->dp.dpq, "RxQ doorbell is %p",
+                             rxq->doorbell);
        sfc_ef10_essb_rx_info(&rxq->dp.dpq,
                              "block size is %u, buf stride is %u",
                              rxq->block_size, rxq->buf_stride);
@@ -618,6 +645,7 @@ fail_desc_alloc:
 fail_rxq_alloc:
 fail_no_block_dequeue:
 fail_get_contig_block_size:
+fail_nic_dma:
        return rc;
 }
 
@@ -633,10 +661,18 @@ sfc_ef10_essb_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 
 static sfc_dp_rx_qstart_t sfc_ef10_essb_rx_qstart;
 static int
-sfc_ef10_essb_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
+sfc_ef10_essb_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr,
+                       const efx_rx_prefix_layout_t *pinfo)
 {
        struct sfc_ef10_essb_rxq *rxq = sfc_ef10_essb_rxq_by_dp_rxq(dp_rxq);
 
+       if (pinfo->erpl_length != sfc_ef10_essb_rx_prefix_layout.erpl_length)
+               return ENOTSUP;
+
+       if (efx_rx_prefix_layout_check(pinfo,
+                                      &sfc_ef10_essb_rx_prefix_layout) != 0)
+               return ENOTSUP;
+
        rxq->evq_read_ptr = evq_read_ptr;
 
        /* Initialize before refill */
@@ -715,7 +751,8 @@ struct sfc_dp_rx sfc_ef10_essb_rx = {
        },
        .features               = SFC_DP_RX_FEAT_FLOW_FLAG |
                                  SFC_DP_RX_FEAT_FLOW_MARK,
-       .dev_offload_capa       = DEV_RX_OFFLOAD_CHECKSUM,
+       .dev_offload_capa       = RTE_ETH_RX_OFFLOAD_CHECKSUM |
+                                 RTE_ETH_RX_OFFLOAD_RSS_HASH,
        .queue_offload_capa     = 0,
        .get_dev_info           = sfc_ef10_essb_rx_get_dev_info,
        .pool_ops_supported     = sfc_ef10_essb_rx_pool_ops_supported,