regex/mlx5: support combined rule file

[dpdk.git] / drivers / regex / mlx5 / mlx5_regex.c

diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index 605ebcf..f1fd911 100644 (file)
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -119,6 +119,7 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
        struct mlx5_hca_attr attr;
        char name[RTE_REGEXDEV_NAME_MAX_LEN];
        int ret;
+       uint32_t val;
 
        ibv = mlx5_regex_get_ib_device_match(&pci_dev->addr);
        if (!ibv) {
@@ -157,10 +158,18 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
        if (!priv) {
                DRV_LOG(ERR, "Failed to allocate private memory.");
                rte_errno = ENOMEM;
-               goto error;
+               goto dev_error;
        }
        priv->ctx = ctx;
        priv->nb_engines = 2; /* attr.regexp_num_of_engines */
+       ret = mlx5_devx_regex_register_read(priv->ctx, 0,
+                                           MLX5_RXP_CSR_IDENTIFIER, &val);
+       if (ret) {
+               DRV_LOG(ERR, "CSR read failed!");
+               return -1;
+       }
+       if (val == MLX5_RXP_BF2_IDENTIFIER)
+               priv->is_bf2 = 1;
        /* Default RXP programming mode to Shared. */
        priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;
        mlx5_regex_get_name(name, pci_dev);
@@ -170,13 +179,12 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
                rte_errno = rte_errno ? rte_errno : EINVAL;
                goto error;
        }
-       ret = mlx5_glue->devx_query_eqn(ctx, 0, &priv->eqn);
-       if (ret) {
-               DRV_LOG(ERR, "can't query event queue number.");
-               rte_errno = ENOMEM;
-               goto error;
-       }
-       priv->uar = mlx5_glue->devx_alloc_uar(ctx, 0);
+       /*
+        * This PMD always claims the write memory barrier on UAR
+        * registers writings, it is safe to allocate UAR with any
+        * memory mapping type.
+        */
+       priv->uar = mlx5_devx_alloc_uar(ctx, -1);
        if (!priv->uar) {
                DRV_LOG(ERR, "can't allocate uar.");
                rte_errno = ENOMEM;
@@ -194,6 +202,16 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
        priv->regexdev->device = (struct rte_device *)pci_dev;
        priv->regexdev->data->dev_private = priv;
        priv->regexdev->state = RTE_REGEXDEV_READY;
+       priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
+       priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
+       ret = mlx5_mr_btree_init(&priv->mr_scache.cache,
+                                MLX5_MR_BTREE_CACHE_N * 2,
+                                rte_socket_id());
+       if (ret) {
+               DRV_LOG(ERR, "MR init tree failed.");
+           rte_errno = ENOMEM;
+               goto error;
+       }
        return 0;
 
 error:
@@ -244,6 +262,10 @@ static const struct rte_pci_id mlx5_regex_pci_id_map[] = {
                RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
                                PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
        },
+       {
+               RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
+                               PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
+       },
        {
                .vendor_id = 0
        }