#include <rte_malloc.h>
#include <rte_log.h>
#include <rte_errno.h>
-#include <rte_bus_pci.h>
#include <rte_pci.h>
#include <rte_regexdev.h>
#include <rte_regexdev_core.h>
#include <rte_regexdev_driver.h>
+#include <mlx5_common_pci.h>
#include <mlx5_glue.h>
#include <mlx5_devx_cmds.h>
#include <mlx5_prm.h>
#include "mlx5_regex_utils.h"
#include "mlx5_rxp_csrs.h"
+#define MLX5_REGEX_DRIVER_NAME regex_mlx5
+#define MLX5_REGEX_LOG_NAME pmd.regex.mlx5
+
int mlx5_regex_logtype;
const struct rte_regexdev_ops mlx5_regexdev_ops = {
.dev_configure = mlx5_regex_configure,
.dev_db_import = mlx5_regex_rules_db_import,
.dev_qp_setup = mlx5_regex_qp_setup,
+ .dev_start = mlx5_regex_start,
+ .dev_stop = mlx5_regex_stop,
+ .dev_close = mlx5_regex_close,
};
+int
+mlx5_regex_start(struct rte_regexdev *dev __rte_unused)
+{
+ return 0;
+}
+
+int
+mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
+{
+ return 0;
+}
+
+int
+mlx5_regex_close(struct rte_regexdev *dev __rte_unused)
+{
+ return 0;
+}
+
static struct ibv_device *
mlx5_regex_get_ib_device_match(struct rte_pci_addr *addr)
{
struct mlx5_hca_attr attr;
char name[RTE_REGEXDEV_NAME_MAX_LEN];
int ret;
+ uint32_t val;
ibv = mlx5_regex_get_ib_device_match(&pci_dev->addr);
if (!ibv) {
if (ret) {
DRV_LOG(ERR, "Unable to read HCA capabilities.");
rte_errno = ENOTSUP;
- goto error;
+ goto dev_error;
} else if (!attr.regex || attr.regexp_num_of_engines == 0) {
DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe "
"old FW/OFED version?");
rte_errno = ENOTSUP;
- goto error;
+ goto dev_error;
}
if (mlx5_regex_engines_status(ctx, 2)) {
DRV_LOG(ERR, "RegEx engine error.");
rte_errno = ENOMEM;
- goto error;
+ goto dev_error;
}
priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv),
RTE_CACHE_LINE_SIZE);
if (!priv) {
DRV_LOG(ERR, "Failed to allocate private memory.");
rte_errno = ENOMEM;
- goto error;
+ goto dev_error;
}
priv->ctx = ctx;
priv->nb_engines = 2; /* attr.regexp_num_of_engines */
+ ret = mlx5_devx_regex_register_read(priv->ctx, 0,
+ MLX5_RXP_CSR_IDENTIFIER, &val);
+ if (ret) {
+ DRV_LOG(ERR, "CSR read failed!");
+ return -1;
+ }
+ if (val == MLX5_RXP_BF2_IDENTIFIER)
+ priv->is_bf2 = 1;
/* Default RXP programming mode to Shared. */
priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;
mlx5_regex_get_name(name, pci_dev);
rte_errno = rte_errno ? rte_errno : EINVAL;
goto error;
}
- ret = mlx5_glue->devx_query_eqn(ctx, 0, &priv->eqn);
- if (ret) {
- DRV_LOG(ERR, "can't query event queue number.");
- rte_errno = ENOMEM;
- goto error;
- }
- priv->uar = mlx5_glue->devx_alloc_uar(ctx, 0);
+ /*
+ * This PMD always claims the write memory barrier on UAR
+ * registers writings, it is safe to allocate UAR with any
+ * memory mapping type.
+ */
+ priv->uar = mlx5_devx_alloc_uar(ctx, -1);
if (!priv->uar) {
DRV_LOG(ERR, "can't allocate uar.");
rte_errno = ENOMEM;
goto error;
}
priv->regexdev->dev_ops = &mlx5_regexdev_ops;
+ priv->regexdev->enqueue = mlx5_regexdev_enqueue;
+ priv->regexdev->dequeue = mlx5_regexdev_dequeue;
priv->regexdev->device = (struct rte_device *)pci_dev;
priv->regexdev->data->dev_private = priv;
priv->regexdev->state = RTE_REGEXDEV_READY;
+ priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
+ priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
+ ret = mlx5_mr_btree_init(&priv->mr_scache.cache,
+ MLX5_MR_BTREE_CACHE_N * 2,
+ rte_socket_id());
+ if (ret) {
+ DRV_LOG(ERR, "MR init tree failed.");
+ rte_errno = ENOMEM;
+ goto error;
+ }
return 0;
error:
mlx5_glue->devx_free_uar(priv->uar);
if (priv->regexdev)
rte_regexdev_unregister(priv->regexdev);
+dev_error:
if (ctx)
mlx5_glue->close_device(ctx);
if (priv)
RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
},
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
+ PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
+ },
{
.vendor_id = 0
}
};
-static struct rte_pci_driver mlx5_regex_driver = {
- .driver = {
- .name = "mlx5_regex",
+static struct mlx5_pci_driver mlx5_regex_driver = {
+ .driver_class = MLX5_CLASS_REGEX,
+ .pci_driver = {
+ .driver = {
+ .name = RTE_STR(MLX5_REGEX_DRIVER_NAME),
+ },
+ .id_table = mlx5_regex_pci_id_map,
+ .probe = mlx5_regex_pci_probe,
+ .remove = mlx5_regex_pci_remove,
+ .drv_flags = 0,
},
- .id_table = mlx5_regex_pci_id_map,
- .probe = mlx5_regex_pci_probe,
- .remove = mlx5_regex_pci_remove,
- .drv_flags = 0,
};
RTE_INIT(rte_mlx5_regex_init)
{
+ mlx5_common_init();
if (mlx5_glue)
- rte_pci_register(&mlx5_regex_driver);
+ mlx5_pci_driver_register(&mlx5_regex_driver);
}
-RTE_LOG_REGISTER(mlx5_regex_logtype, pmd.regex.mlx5, NOTICE)
-RTE_PMD_EXPORT_NAME(net_mlx5_regex, __COUNTER__);
-RTE_PMD_REGISTER_PCI_TABLE(net_mlx5_regex, mlx5_regex_pci_id_map);
-RTE_PMD_REGISTER_KMOD_DEP(net_mlx5_regex, "* ib_uverbs & mlx5_core & mlx5_ib");
+RTE_LOG_REGISTER(mlx5_regex_logtype, MLX5_REGEX_LOG_NAME, NOTICE)
+RTE_PMD_EXPORT_NAME(MLX5_REGEX_DRIVER_NAME, __COUNTER__);
+RTE_PMD_REGISTER_PCI_TABLE(MLX5_REGEX_DRIVER_NAME, mlx5_regex_pci_id_map);
+RTE_PMD_REGISTER_KMOD_DEP(MLX5_REGEX_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");
git.droids-corp.org / dpdk.git / blobdiff