for (n = 0; n < config->num_fields; n++) {
double wild = 0;
+ uint64_t msk_val =
+ RTE_LEN2MASK(CHAR_BIT * config->defs[n].size,
+ typeof(msk_val));
double size = CHAR_BIT * config->defs[n].size;
int field_index = config->defs[n].field_index;
const struct rte_acl_field *fld = rule->f->field +
switch (rule->config->defs[n].type) {
case RTE_ACL_FIELD_TYPE_BITMASK:
- wild = (size - __builtin_popcount(
- fld->mask_range.u8)) /
+ wild = (size - __builtin_popcountll(
+ fld->mask_range.u64 & msk_val)) /
size;
break;
bcx->pool.alignment = ACL_POOL_ALIGN;
bcx->pool.min_alloc = ACL_POOL_ALLOC_MIN;
bcx->cfg = *cfg;
- bcx->category_mask = LEN2MASK(bcx->cfg.num_categories);
+ bcx->category_mask = RTE_LEN2MASK(bcx->cfg.num_categories,
+ typeof(bcx->category_mask));
bcx->node_max = node_max;
rc = sigsetjmp(bcx->pool.fail, 0);