/*
* BSD LICENSE
*
- * Copyright (C) Cavium networks Ltd. 2015.
+ * Copyright (C) Cavium, Inc. 2015.
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
- * * Neither the name of Cavium networks nor the names of its
+ * * Neither the name of Cavium, Inc nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
#endif
enum cpu_register_t {
- REG_HWCAP = 0,
+ REG_NONE = 0,
+ REG_HWCAP,
REG_HWCAP2,
REG_PLATFORM,
+ REG_MAX
};
-typedef uint32_t cpuid_registers_t[4];
+typedef uint32_t hwcap_registers_t[REG_MAX];
/**
* Struct to hold a processor feature entry
*/
struct feature_entry {
- uint32_t leaf; /**< cpuid leaf */
- uint32_t subleaf; /**< cpuid subleaf */
- uint32_t reg; /**< cpuid register */
- uint32_t bit; /**< cpuid register bit */
+ uint32_t reg;
+ uint32_t bit;
#define CPU_FLAG_NAME_MAX_LEN 64
- char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
+ char name[CPU_FLAG_NAME_MAX_LEN];
};
-#define FEAT_DEF(name, leaf, subleaf, reg, bit) \
- [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
+#define FEAT_DEF(name, reg, bit) \
+ [RTE_CPUFLAG_##name] = {reg, bit, #name},
#ifdef RTE_ARCH_ARMv7
#define PLATFORM_STR "v7l"
typedef Elf32_auxv_t _Elfx_auxv_t;
const struct feature_entry rte_cpu_feature_table[] = {
- FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0)
- FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1)
- FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2)
- FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3)
- FEAT_DEF(FAST_MULT, 0x00000001, 0, REG_HWCAP, 4)
- FEAT_DEF(FPA, 0x00000001, 0, REG_HWCAP, 5)
- FEAT_DEF(VFP, 0x00000001, 0, REG_HWCAP, 6)
- FEAT_DEF(EDSP, 0x00000001, 0, REG_HWCAP, 7)
- FEAT_DEF(JAVA, 0x00000001, 0, REG_HWCAP, 8)
- FEAT_DEF(IWMMXT, 0x00000001, 0, REG_HWCAP, 9)
- FEAT_DEF(CRUNCH, 0x00000001, 0, REG_HWCAP, 10)
- FEAT_DEF(THUMBEE, 0x00000001, 0, REG_HWCAP, 11)
- FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 12)
- FEAT_DEF(VFPv3, 0x00000001, 0, REG_HWCAP, 13)
- FEAT_DEF(VFPv3D16, 0x00000001, 0, REG_HWCAP, 14)
- FEAT_DEF(TLS, 0x00000001, 0, REG_HWCAP, 15)
- FEAT_DEF(VFPv4, 0x00000001, 0, REG_HWCAP, 16)
- FEAT_DEF(IDIVA, 0x00000001, 0, REG_HWCAP, 17)
- FEAT_DEF(IDIVT, 0x00000001, 0, REG_HWCAP, 18)
- FEAT_DEF(VFPD32, 0x00000001, 0, REG_HWCAP, 19)
- FEAT_DEF(LPAE, 0x00000001, 0, REG_HWCAP, 20)
- FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 21)
- FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP2, 0)
- FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP2, 1)
- FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2)
- FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3)
- FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4)
- FEAT_DEF(V7L, 0x00000001, 0, REG_PLATFORM, 0)
+ FEAT_DEF(SWP, REG_HWCAP, 0)
+ FEAT_DEF(HALF, REG_HWCAP, 1)
+ FEAT_DEF(THUMB, REG_HWCAP, 2)
+ FEAT_DEF(A26BIT, REG_HWCAP, 3)
+ FEAT_DEF(FAST_MULT, REG_HWCAP, 4)
+ FEAT_DEF(FPA, REG_HWCAP, 5)
+ FEAT_DEF(VFP, REG_HWCAP, 6)
+ FEAT_DEF(EDSP, REG_HWCAP, 7)
+ FEAT_DEF(JAVA, REG_HWCAP, 8)
+ FEAT_DEF(IWMMXT, REG_HWCAP, 9)
+ FEAT_DEF(CRUNCH, REG_HWCAP, 10)
+ FEAT_DEF(THUMBEE, REG_HWCAP, 11)
+ FEAT_DEF(NEON, REG_HWCAP, 12)
+ FEAT_DEF(VFPv3, REG_HWCAP, 13)
+ FEAT_DEF(VFPv3D16, REG_HWCAP, 14)
+ FEAT_DEF(TLS, REG_HWCAP, 15)
+ FEAT_DEF(VFPv4, REG_HWCAP, 16)
+ FEAT_DEF(IDIVA, REG_HWCAP, 17)
+ FEAT_DEF(IDIVT, REG_HWCAP, 18)
+ FEAT_DEF(VFPD32, REG_HWCAP, 19)
+ FEAT_DEF(LPAE, REG_HWCAP, 20)
+ FEAT_DEF(EVTSTRM, REG_HWCAP, 21)
+ FEAT_DEF(AES, REG_HWCAP2, 0)
+ FEAT_DEF(PMULL, REG_HWCAP2, 1)
+ FEAT_DEF(SHA1, REG_HWCAP2, 2)
+ FEAT_DEF(SHA2, REG_HWCAP2, 3)
+ FEAT_DEF(CRC32, REG_HWCAP2, 4)
+ FEAT_DEF(V7L, REG_PLATFORM, 0)
};
#elif defined RTE_ARCH_ARM64
typedef Elf64_auxv_t _Elfx_auxv_t;
const struct feature_entry rte_cpu_feature_table[] = {
- FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP, 0)
- FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 1)
- FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 2)
- FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP, 3)
- FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP, 4)
- FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP, 5)
- FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP, 6)
- FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP, 7)
- FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1)
+ FEAT_DEF(FP, REG_HWCAP, 0)
+ FEAT_DEF(NEON, REG_HWCAP, 1)
+ FEAT_DEF(EVTSTRM, REG_HWCAP, 2)
+ FEAT_DEF(AES, REG_HWCAP, 3)
+ FEAT_DEF(PMULL, REG_HWCAP, 4)
+ FEAT_DEF(SHA1, REG_HWCAP, 5)
+ FEAT_DEF(SHA2, REG_HWCAP, 6)
+ FEAT_DEF(CRC32, REG_HWCAP, 7)
+ FEAT_DEF(ATOMICS, REG_HWCAP, 8)
+ FEAT_DEF(AARCH64, REG_PLATFORM, 1)
};
#endif /* RTE_ARCH */
* Read AUXV software register and get cpu features for ARM
*/
static void
-rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
- __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
+rte_cpu_get_features(hwcap_registers_t out)
{
int auxv_fd;
_Elfx_auxv_t auxv;
out[REG_PLATFORM] = 0x0001;
}
}
+ close(auxv_fd);
}
/*
rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
{
const struct feature_entry *feat;
- cpuid_registers_t regs = {0};
+ hwcap_registers_t regs = {0};
if (feature >= RTE_CPUFLAG_NUMFLAGS)
- /* Flag does not match anything in the feature tables */
return -ENOENT;
feat = &rte_cpu_feature_table[feature];
-
- if (!feat->leaf)
- /* This entry in the table wasn't filled out! */
+ if (feat->reg == REG_NONE)
return -EFAULT;
- /* get the cpuid leaf containing the desired feature */
- rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
-
- /* check if the feature is enabled */
+ rte_cpu_get_features(regs);
return (regs[feat->reg] >> feat->bit) & 1;
}
git.droids-corp.org / dpdk.git / blobdiff