#include <rte_config.h>
#include <rte_ether.h>
+#include "rte_ethdev_trace_fp.h"
#include "rte_dev_info.h"
extern int rte_eth_dev_logtype;
uint16_t link_duplex : 1; /**< ETH_LINK_[HALF/FULL]_DUPLEX */
uint16_t link_autoneg : 1; /**< ETH_LINK_[AUTONEG/FIXED] */
uint16_t link_status : 1; /**< ETH_LINK_[DOWN/UP] */
-} __attribute__((aligned(8))); /**< aligned for atomic64 read/write */
+} __rte_aligned(8); /**< aligned for atomic64 read/write */
/* Utility constants */
#define ETH_LINK_HALF_DUPLEX 0 /**< Half-duplex connection (see link_duplex). */
/** The multi-queue packet distribution mode to be used, e.g. RSS. */
enum rte_eth_rx_mq_mode mq_mode;
uint32_t max_rx_pkt_len; /**< Only used if JUMBO_FRAME enabled. */
+ /** Maximum allowed size of LRO aggregated packet. */
+ uint32_t max_lro_pkt_size;
uint16_t split_hdr_size; /**< hdr buf size (header_split enabled).*/
/**
* Per-port Rx offloads to be set using DEV_RX_OFFLOAD_* flags.
* structure are allowed to be set.
*/
uint64_t offloads;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
#define ETH_RSS_GENEVE (1ULL << 20)
#define ETH_RSS_NVGRE (1ULL << 21)
#define ETH_RSS_GTPU (1ULL << 23)
+#define ETH_RSS_ETH (1ULL << 24)
+#define ETH_RSS_S_VLAN (1ULL << 25)
+#define ETH_RSS_C_VLAN (1ULL << 26)
+#define ETH_RSS_ESP (1ULL << 27)
+#define ETH_RSS_AH (1ULL << 28)
+#define ETH_RSS_L2TPV3 (1ULL << 29)
+#define ETH_RSS_PFCP (1ULL << 30)
+
/*
* We use the following macros to combine with above ETH_RSS_* for
#define ETH_RSS_L3_DST_ONLY (1ULL << 62)
#define ETH_RSS_L4_SRC_ONLY (1ULL << 61)
#define ETH_RSS_L4_DST_ONLY (1ULL << 60)
+#define ETH_RSS_L2_SRC_ONLY (1ULL << 59)
+#define ETH_RSS_L2_DST_ONLY (1ULL << 58)
/**
* For input set change of hash filter, if SRC_ONLY and DST_ONLY of
ETH_RSS_GENEVE | \
ETH_RSS_NVGRE)
+#define ETH_RSS_VLAN ( \
+ ETH_RSS_S_VLAN | \
+ ETH_RSS_C_VLAN)
+
/**< Mask of valid RSS hash protocols */
#define ETH_RSS_PROTO_MASK ( \
ETH_RSS_IPV4 | \
/**< If set, reject sending out untagged pkts */
hw_vlan_insert_pvid : 1;
/**< If set, enable port based VLAN insertion */
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
* fields on rte_eth_dev_info structure are allowed to be set.
*/
uint64_t offloads;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
* fields on rte_eth_dev_info structure are allowed to be set.
*/
uint64_t offloads;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
* Default values for switch domain id when ethdev does not support switch
* domain definitions.
*/
-#define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (0)
+#define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (UINT16_MAX)
/**
* Ethernet device associated switch information
const uint32_t *dev_flags; /**< Device flags */
uint32_t min_rx_bufsize; /**< Minimum size of RX buffer. */
uint32_t max_rx_pktlen; /**< Maximum configurable length of RX pkt. */
+ /** Maximum configurable size of LRO aggregated packet. */
+ uint32_t max_lro_pkt_size;
uint16_t max_rx_queues; /**< Maximum number of RX queues. */
uint16_t max_tx_queues; /**< Maximum number of TX queues. */
uint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */
* embedded managed interconnect/switch.
*/
struct rte_eth_switch_info switch_info;
+
+ uint64_t reserved_64s[2]; /**< Reserved for future fields */
+ void *reserved_ptrs[2]; /**< Reserved for future fields */
};
/**
RTE_ETH_EVENT_NEW, /**< port is probed */
RTE_ETH_EVENT_DESTROY, /**< port is released */
RTE_ETH_EVENT_IPSEC, /**< IPsec offload related event */
+ RTE_ETH_EVENT_FLOW_AGED,/**< New aged-out flows is detected */
RTE_ETH_EVENT_MAX /**< max value of this enum */
};
}
#endif
+ rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts, nb_rx);
return nb_rx;
}
}
#endif
+ rte_ethdev_trace_tx_burst(port_id, queue_id, (void **)tx_pkts,
+ nb_pkts);
return (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id], tx_pkts, nb_pkts);
}