+parse_max_pools(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint32_t val;
+
+ val = atoi(value);
+ if (val < npa_aura_size_to_u32(NPA_AURA_SZ_128))
+ val = 128;
+ if (val > npa_aura_size_to_u32(NPA_AURA_SZ_1M))
+ val = BIT_ULL(20);
+
+ *(uint8_t *)extra_args = rte_log2_u32(val) - 6;
+ return 0;
+}
+
+static inline uint8_t
+parse_aura_size(struct rte_devargs *devargs)
+{
+ uint8_t aura_sz = NPA_AURA_SZ_128;
+ struct rte_kvargs *kvlist;
+
+ if (devargs == NULL)
+ goto exit;
+ kvlist = rte_kvargs_parse(devargs->args, NULL);
+ if (kvlist == NULL)
+ goto exit;
+
+ rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools,
+ &aura_sz);
+ rte_kvargs_free(kvlist);
+exit:
+ return aura_sz;
+}
+
+static inline char *
+npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)
+{
+ snprintf(name, CNXK_NPA_DEV_NAME_LEN, CNXK_NPA_DEV_NAME PCI_PRI_FMT,
+ pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid,
+ pci_dev->addr.function);
+
+ return name;
+}
+
+static int
+npa_init(struct rte_pci_device *pci_dev)