The structure size is u64 so it could be used with single cpu operation.
Test report: http://www.dpdk.org/ml/archives/dev/2015-March/014467.html
Signed-off-by: Jijiang Liu <jijiang.liu@intel.com>
Signed-off-by: Miroslaw Walukiewicz <miroslaw.walukiewicz@intel.com>
Signed-off-by: Grzegorz Galkowski <grzegorz.galkowski@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Tested-by: Min Cao <min.cao@intel.com>
i40e_txd_enable_checksum(uint64_t ol_flags,
uint32_t *td_cmd,
uint32_t *td_offset,
i40e_txd_enable_checksum(uint64_t ol_flags,
uint32_t *td_cmd,
uint32_t *td_offset,
- uint8_t l2_len,
- uint16_t l3_len,
- uint8_t outer_l2_len,
- uint16_t outer_l3_len,
+ union i40e_tx_offload tx_offload,
uint32_t *cd_tunneling)
{
/* UDP tunneling packet TX checksum offload */
if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
uint32_t *cd_tunneling)
{
/* UDP tunneling packet TX checksum offload */
if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
- *td_offset |= (outer_l2_len >> 1)
+ *td_offset |= (tx_offload.outer_l2_len >> 1)
<< I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
<< I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
/* Now set the ctx descriptor fields */
*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
/* Now set the ctx descriptor fields */
- *cd_tunneling |= (outer_l3_len >> 2) <<
+ *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
+ (tx_offload.l2_len >> 1) <<
I40E_TXD_CTX_QW0_NATLEN_SHIFT;
} else
I40E_TXD_CTX_QW0_NATLEN_SHIFT;
} else
- *td_offset |= (l2_len >> 1)
+ *td_offset |= (tx_offload.l2_len >> 1)
<< I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
/* Enable L3 checksum offloads */
if (ol_flags & PKT_TX_IP_CKSUM) {
*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
<< I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
/* Enable L3 checksum offloads */
if (ol_flags & PKT_TX_IP_CKSUM) {
*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
- *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
+ *td_offset |= (tx_offload.l3_len >> 2)
+ << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
} else if (ol_flags & PKT_TX_IPV4) {
*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
} else if (ol_flags & PKT_TX_IPV4) {
*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
- *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
+ *td_offset |= (tx_offload.l3_len >> 2)
+ << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
} else if (ol_flags & PKT_TX_IPV6) {
*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
} else if (ol_flags & PKT_TX_IPV6) {
*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
- *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
+ *td_offset |= (tx_offload.l3_len >> 2)
+ << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
}
/* Enable L4 checksum offloads */
}
/* Enable L4 checksum offloads */
uint32_t tx_flags;
uint32_t td_tag;
uint64_t ol_flags;
uint32_t tx_flags;
uint32_t td_tag;
uint64_t ol_flags;
- uint8_t l2_len;
- uint16_t l3_len;
- uint8_t outer_l2_len;
- uint16_t outer_l3_len;
uint16_t nb_used;
uint16_t nb_ctx;
uint16_t tx_last;
uint16_t slen;
uint64_t buf_dma_addr;
uint16_t nb_used;
uint16_t nb_ctx;
uint16_t tx_last;
uint16_t slen;
uint64_t buf_dma_addr;
+ union i40e_tx_offload tx_offload = { .data = 0 };
txq = tx_queue;
sw_ring = txq->sw_ring;
txq = tx_queue;
sw_ring = txq->sw_ring;
RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
ol_flags = tx_pkt->ol_flags;
RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
ol_flags = tx_pkt->ol_flags;
- l2_len = tx_pkt->l2_len;
- l3_len = tx_pkt->l3_len;
- outer_l2_len = tx_pkt->outer_l2_len;
- outer_l3_len = tx_pkt->outer_l3_len;
+ tx_offload.l2_len = tx_pkt->l2_len;
+ tx_offload.l3_len = tx_pkt->l3_len;
+ tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
+ tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
/* Calculate the number of context descriptors needed. */
nb_ctx = i40e_calc_context_desc(ol_flags);
/* Calculate the number of context descriptors needed. */
nb_ctx = i40e_calc_context_desc(ol_flags);
cd_tunneling_params = 0;
if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
cd_tunneling_params = 0;
if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
- l2_len, l3_len, outer_l2_len,
- outer_l3_len,
- &cd_tunneling_params);
+ tx_offload, &cd_tunneling_params);
}
if (unlikely(nb_ctx)) {
}
if (unlikely(nb_ctx)) {
bool tx_deferred_start; /**< don't start this queue in dev start */
};
bool tx_deferred_start; /**< don't start this queue in dev start */
};
+/** Offload features */
+union i40e_tx_offload {
+ uint64_t data;
+ struct {
+ uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
+ uint64_t l3_len:9; /**< L3 (IP) Header Length. */
+ uint64_t outer_l2_len:8; /**< outer L2 Header Length */
+ uint64_t outer_l3_len:16; /**< outer L3 Header Length */
+ };
+};
+
int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);