Phy capabilities are bit offsets in libefx, but was used as bit masks.
Fixes:
d23f3a89ab54 ("net/sfc: support link speed and duplex settings")
Fixes:
f82e33afbbb9 ("net/sfc: support link speeds up to 100G")
Cc: stable@dpdk.org
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
/* Autonegotiation may be disabled */
dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
/* Autonegotiation may be disabled */
dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_1000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_1G;
dev_info->speed_capa |= ETH_LINK_SPEED_1G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_10000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_10G;
dev_info->speed_capa |= ETH_LINK_SPEED_10G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_25000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_25G;
dev_info->speed_capa |= ETH_LINK_SPEED_25G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_40000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_40G;
dev_info->speed_capa |= ETH_LINK_SPEED_40G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_50000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_50G;
dev_info->speed_capa |= ETH_LINK_SPEED_50G;
- if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_100000FDX)
+ if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX))
dev_info->speed_capa |= ETH_LINK_SPEED_100G;
dev_info->max_rx_queues = sa->rxq_max;
dev_info->speed_capa |= ETH_LINK_SPEED_100G;
dev_info->max_rx_queues = sa->rxq_max;