Program the PCIe completion timeout to 4 sec to give enough time
to allow completions to be received successfully in some older systems.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_CAPABILITY_LIST 0x34
/* Offset of first capability list entry */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_CAPABILITY_LIST 0x34
/* Offset of first capability list entry */
+#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
+#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
/**
* t4_os_pci_write_cfg4 - 32-bit write to PCI config space
/**
* t4_os_pci_write_cfg4 - 32-bit write to PCI config space
- * Copyright(c) 2014-2015 Chelsio Communications.
+ * Copyright(c) 2014-2016 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
+static void set_pcie_completion_timeout(struct adapter *adapter,
+ u8 range)
+{
+ u32 pcie_cap;
+ u16 val;
+
+ pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
+ if (pcie_cap) {
+ t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
+ val &= 0xfff0;
+ val |= range;
+ t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
+ }
+}
+
/**
* t4_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
/**
* t4_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
adapter->params.portvec = 1;
adapter->params.vpd.cclk = 50000;
adapter->params.portvec = 1;
adapter->params.vpd.cclk = 50000;
+ /* Set pci completion timeout value to 4 seconds. */
+ set_pcie_completion_timeout(adapter, 0xd);