net/iavf: enable PCI bus master after reset

The VF reset can be triggered by the PF reset event, then the PCI bus
master will be cleared, the VF will be not allowed to issue any Memory
or I/O Requests.

So after the reset event is detected, always enable the PCI bus master.
And if failed, the device or system may be in an invalid state, so keep
the VF reset state to mark it as I/O error.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index d688c31..a7ef7a6 100644 (file)
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -2356,7 +2356,15 @@ iavf_dev_close(struct rte_eth_dev *dev)
        rte_free(vf->aq_resp);
        vf->aq_resp = NULL;
 
-       vf->vf_reset = false;
+       /*
+        * If the VF is reset via VFLR, the device will be knocked out of bus
+        * master mode, and the driver will fail to recover from the reset. Fix
+        * this by enabling bus mastering after every reset. In a non-VFLR case,
+        * the bus master bit will not be disabled, and this call will have no
+        * effect.
+        */
+       if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))
+               vf->vf_reset = false;
 
        return ret;
 }