doc: fix flow integrity hardware support in mlx5 guide
authorGregory Etelson <getelson@nvidia.com>
Thu, 16 Jun 2022 08:43:14 +0000 (11:43 +0300)
committerRaslan Darawsheh <rasland@nvidia.com>
Thu, 23 Jun 2022 15:25:08 +0000 (17:25 +0200)
Current MLX5 PMD documentation says that entire `ConnectX-6` family
supports flow integrity feature.

Flow integrity offload is not supported on vanilla `ConnectX-6`.
It is available on `ConnectX-6 Dx`, `ConnectX-6 Lx` and
`BlueField 2`.

Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
doc/guides/nics/mlx5.rst

index 915467d..bc2bd2c 100644 (file)
@@ -476,7 +476,7 @@ Limitations
 
 - Integrity:
 
-  - Integrity offload is enabled for **ConnectX-6** family.
+  - Integrity offload is enabled starting from **ConnectX-6 Dx**.
   - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
   - ``level`` value 0 references outer headers.
   - Multiple integrity items not supported in a single flow rule.