net/e1000/base: support MAC type for Nahum10

Add support to a new MAC type (for Nahum10).

Signed-off-by: Roman Fridlyand <roman.fridlyand@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>

diff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h
index b71cb4d..11acec2 100644 (file)
--- a/drivers/net/e1000/base/e1000_hw.h
+++ b/drivers/net/e1000/base/e1000_hw.h
@@ -212,6 +212,7 @@ enum e1000_mac_type {
        e1000_pch_lpt,
        e1000_pch_spt,
        e1000_pch_cnp,
+       e1000_pch_adp,
        e1000_82575,
        e1000_82576,
        e1000_82580,

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 85344eb..61dcc1e 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -318,6 +318,7 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
@@ -467,6 +468,7 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                case e1000_pch_lpt:
                case e1000_pch_spt:
                case e1000_pch_cnp:
+               case e1000_pch_adp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
@@ -772,12 +774,11 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
-#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
+       case e1000_pch_adp:
                /* multicast address update for pch2 */
                mac->ops.update_mc_addr_list =
                        e1000_update_mc_addr_list_pch2lan;
                /* fall-through */
-#endif
        case e1000_pchlan:
 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
                /* save PCH revision_id */
@@ -1764,6 +1765,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
                break;
        default:
@@ -2231,6 +2233,7 @@ STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -3358,6 +3361,7 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
        switch (hw->mac.type) {
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
@@ -4329,6 +4333,7 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_adp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;