event/octeontx2: configure crypto adapter xaq pool

Configure xaq pool based on number of in-use crypto queues to avoid CPT
add work failure due to xaq buffer run out. This patch configures
OTX2_CPT_DEFAULT_CMD_QLEN number of xae entries per queue pair.

Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework")
Cc: stable@dpdk.org
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>

diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c
index d69f269..d85c366 100644 (file)
--- a/drivers/event/octeontx2/otx2_evdev_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_adptr.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
+ * Copyright(C) 2019-2021 Marvell.
  */
 
 #include "otx2_evdev.h"

diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
index ed600a6..d9a0026 100644 (file)
--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
@@ -89,6 +89,14 @@ otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
        sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;
        sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);
 
+       /* Update crypto adapter xae count */
+       if (queue_pair_id == -1)
+               sso_evdev->adptr_xae_cnt +=
+                       vf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN;
+       else
+               sso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN;
+       sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev);
+
        return 0;
 }