nicvf_reg_write(nic, NIC_VNIC_RQ_GEN_CFG, val);
}
+void
+nicvf_apad_config(struct nicvf *nic, bool enable)
+{
+ uint64_t val;
+
+ /* APAD always enabled in this device */
+ if (!(nic->hwcap & NICVF_CAP_DISABLE_APAD))
+ return;
+
+ val = nicvf_reg_read(nic, NIC_VNIC_RQ_GEN_CFG);
+ if (enable)
+ val &= ~(1ULL << NICVF_QS_RQ_DIS_APAD_SHIFT);
+ else
+ val |= (1ULL << NICVF_QS_RQ_DIS_APAD_SHIFT);
+
+ nicvf_reg_write(nic, NIC_VNIC_RQ_GEN_CFG, val);
+}
+
void
nicvf_rss_set_key(struct nicvf *nic, uint8_t *key)
{
#define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
/* Additional word in Rx descriptor to hold optional tunneling extension info */
#define NICVF_CAP_CQE_RX2 (1ULL << 1)
+/* The device capable of setting NIC_CQE_RX_S[APAD] == 0 */
+#define NICVF_CAP_DISABLE_APAD (1ULL << 2)
enum nicvf_tns_mode {
NIC_TNS_BYPASS_MODE,
void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
+void nicvf_apad_config(struct nicvf *nic, bool enable);
+
int nicvf_rss_config(struct nicvf *nic, uint32_t qcnt, uint64_t cfg);
int nicvf_rss_term(struct nicvf *nic);
#define NICVF_INTR_MBOX_SHIFT 22
#define NICVF_INTR_QS_ERR_SHIFT 23
+#define NICVF_QS_RQ_DIS_APAD_SHIFT 22
+
#define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
#define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
#define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
/* Configure VLAN Strip */
nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
+ /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
+ * to the 64bit memory address.
+ * The alignment creates a hole in mbuf(between the end of headroom and
+ * packet data start). The new revision of the HW provides an option to
+ * disable the L3 alignment feature and make mbuf layout looks
+ * more like other NICs. For better application compatibility, disabling
+ * l3 alignment feature on the hardware revisions it supports
+ */
+ nicvf_apad_config(nic, false);
+
/* Get queue ranges for this VF */
nicvf_tx_range(dev, nic, &tx_start, &tx_end);