net/enetc: relax read for Tx CI in clean Tx
authorAlex Marginean <alexandru.marginean@nxp.com>
Mon, 2 Mar 2020 14:32:01 +0000 (20:02 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Wed, 18 Mar 2020 09:21:41 +0000 (10:21 +0100)
We don't need barriers here since this read doesn't have to be strictly
serialized in relation to other surrounding memory/register accesses.
We only want a reasonably recent value out of hardware so we know how
much we can clean.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Gagandeep Singh <g.singh@nxp.com>

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