common/mlx5: share common definitions

Create MACRO definitions file in the common driver as preparation for MR
and basic probe sharing.
Move relevant definitions from the net driver to the above file.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c
index 91de7b3..8e3ea07 100644 (file)
--- a/drivers/common/mlx5/mlx5_common.c
+++ b/drivers/common/mlx5/mlx5_common.c
@@ -14,6 +14,7 @@
 #include "mlx5_common.h"
 #include "mlx5_common_os.h"
 #include "mlx5_common_log.h"
+#include "mlx5_common_defs.h"
 #include "mlx5_common_private.h"
 
 uint8_t haswell_broadwell_cpu;

diff --git a/drivers/common/mlx5/mlx5_common_defs.h b/drivers/common/mlx5/mlx5_common_defs.h
new file mode 100644 (file)
index 0000000..6fd30f2
--- /dev/null
+++ b/drivers/common/mlx5/mlx5_common_defs.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2021 6WIND S.A.
+ * Copyright 2021 Mellanox Technologies, Ltd
+ */
+
+#ifndef RTE_PMD_MLX5_COMMON_DEFS_H_
+#define RTE_PMD_MLX5_COMMON_DEFS_H_
+
+#include "mlx5_autoconf.h"
+
+/* Size of per-queue MR cache array for linear search. */
+#define MLX5_MR_CACHE_N 8
+
+/* Size of MR cache table for binary search. */
+#define MLX5_MR_BTREE_CACHE_N 256
+
+/*
+ * Defines the amount of retries to allocate the first UAR in the page.
+ * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
+ * UAR base address if UAR was not the first object in the UAR page.
+ * It caused the PMD failure and we should try to get another UAR
+ * till we get the first one with non-NULL base address returned.
+ */
+#define MLX5_ALLOC_UAR_RETRY 32
+
+/* Environment variable to control the doorbell register mapping. */
+#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF"
+#if defined(RTE_ARCH_ARM64)
+#define MLX5_SHUT_UP_BF_DEFAULT "0"
+#else
+#define MLX5_SHUT_UP_BF_DEFAULT "1"
+#endif
+
+/* Default PMD specific parameter value. */
+#define MLX5_ARG_UNSET (-1)
+
+/* MLX5_TX_DB_NC supported values. */
+#define MLX5_TXDB_CACHED 0
+#define MLX5_TXDB_NCACHED 1
+#define MLX5_TXDB_HEURISTIC 2
+
+#endif /* RTE_PMD_MLX5_COMMON_DEFS_H_ */

diff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h
index 685ac98..15489cd 100644 (file)
--- a/drivers/common/mlx5/mlx5_common_mr.h
+++ b/drivers/common/mlx5/mlx5_common_mr.h
@@ -18,10 +18,7 @@
 
 #include "mlx5_glue.h"
 #include "mlx5_common_mp.h"
-
-/* Size of per-queue MR cache array for linear search. */
-#define MLX5_MR_CACHE_N 8
-#define MLX5_MR_BTREE_CACHE_N 256
+#include "mlx5_common_defs.h"
 
 /* mlx5 PMD MR struct. */
 struct mlx5_pmd_mr {

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 6948cad..979bc94 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -5,18 +5,10 @@
 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
 #define RTE_PMD_MLX5_DEVX_CMDS_H_
 
-#include "mlx5_glue.h"
-#include "mlx5_prm.h"
 #include <rte_compat.h>
 
-/*
- * Defines the amount of retries to allocate the first UAR in the page.
- * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
- * UAR base address if UAR was not the first object in the UAR page.
- * It caused the PMD failure and we should try to get another UAR
- * till we get the first one with non-NULL base address returned.
- */
-#define MLX5_ALLOC_UAR_RETRY 32
+#include "mlx5_glue.h"
+#include "mlx5_prm.h"
 
 /* This is limitation of libibverbs: in length variable type is u16. */
 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index fcf22f8..103dee7 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -27,6 +27,7 @@
 #include <mlx5_common_mp.h>
 #include <mlx5_common_mr.h>
 #include <mlx5_common_devx.h>
+#include <mlx5_common_defs.h>
 
 #include "mlx5_defs.h"
 #include "mlx5_utils.h"
@@ -214,9 +215,6 @@ struct mlx5_stats_ctrl {
        uint64_t imissed;
 };
 
-/* Default PMD specific parameter value. */
-#define MLX5_ARG_UNSET (-1)
-
 #define MLX5_LRO_SUPPORTED(dev) \
        (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
 

diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h
index fe86bb4..376e34a 100644 (file)
--- a/drivers/net/mlx5/mlx5_defs.h
+++ b/drivers/net/mlx5/mlx5_defs.h
@@ -9,6 +9,8 @@
 #include <ethdev_driver.h>
 #include <rte_vxlan.h>
 
+#include <mlx5_common_defs.h>
+
 #include "mlx5_autoconf.h"
 
 /* Maximum number of simultaneous VLAN filters. */
@@ -33,13 +35,6 @@
  */
 #define MLX5_TX_COMP_MAX_CQE 2u
 
-
-/* Size of per-queue MR cache array for linear search. */
-#define MLX5_MR_CACHE_N 8
-
-/* Size of MR cache table for binary search. */
-#define MLX5_MR_BTREE_CACHE_N 256
-
 /*
  * If defined, only use software counters. The PMD will never ask the hardware
  * for these, and many of them won't be available.
@@ -121,14 +116,6 @@
 #define MLX5_UAR_MMAP_CMD_SHIFT 8
 #define MLX5_UAR_MMAP_CMD_MASK 0xff
 
-/* Environment variable to control the doorbell register mapping. */
-#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF"
-#if defined(RTE_ARCH_ARM64)
-#define MLX5_SHUT_UP_BF_DEFAULT "0"
-#else
-#define MLX5_SHUT_UP_BF_DEFAULT "1"
-#endif
-
 #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD
 #define MLX5_MMAP_GET_NC_PAGES_CMD 3
 #endif
@@ -161,11 +148,6 @@
 /* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */
 #define MLX5_XMETA_MODE_MISS_INFO 3
 
-/* MLX5_TX_DB_NC supported values. */
-#define MLX5_TXDB_CACHED 0
-#define MLX5_TXDB_NCACHED 1
-#define MLX5_TXDB_HEURISTIC 2
-
 /* Tx accurate scheduling on timestamps parameters. */
 #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */
 #define MLX5_TXPP_CLKQ_SIZE 1