net/ice: use write combining store for tail updates
authorRadu Nicolau <radu.nicolau@intel.com>
Wed, 23 Sep 2020 14:22:53 +0000 (14:22 +0000)
committerDavid Marchand <david.marchand@redhat.com>
Tue, 13 Oct 2020 12:42:02 +0000 (14:42 +0200)
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
doc/guides/rel_notes/release_20_11.rst
drivers/net/ice/base/ice_osdep.h
drivers/net/ice/ice_rxtx.c
drivers/net/ice/ice_rxtx_vec_avx2.c
drivers/net/ice/ice_rxtx_vec_sse.c

index fafd0f7..b7881f2 100644 (file)
@@ -107,6 +107,10 @@ New Features
 
   Updated the Intel ixgbe driver to use write combining stores.
 
+* **Updated Intel ice driver.**
+
+  Updated the Intel ice driver to use write combining stores.
+
 * **Updated Intel qat driver.**
 
   Updated the Intel qat driver to use write combining stores.
index 9a170b5..c0f1e77 100644 (file)
@@ -165,6 +165,7 @@ do {                                                                        \
 #endif
 
 #define ICE_PCI_REG_WRITE(reg, value) writel(value, reg)
+#define ICE_PCI_REG_WC_WRITE(reg, value) rte_write32_wc(value, reg)
 
 #define ICE_READ_REG(hw, reg)         rd32(hw, reg)
 #define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
index 93a0ac6..79e6df1 100644 (file)
@@ -1841,7 +1841,7 @@ ice_recv_scattered_pkts(void *rx_queue,
                rx_id = (uint16_t)(rx_id == 0 ?
                                   (rxq->nb_rx_desc - 1) : (rx_id - 1));
                /* write TAIL register */
-               ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
+               ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
                nb_hold = 0;
        }
        rxq->nb_rx_hold = nb_hold;
@@ -2231,7 +2231,7 @@ ice_recv_pkts(void *rx_queue,
                rx_id = (uint16_t)(rx_id == 0 ?
                                   (rxq->nb_rx_desc - 1) : (rx_id - 1));
                /* write TAIL register */
-               ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
+               ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
                nb_hold = 0;
        }
        rxq->nb_rx_hold = nb_hold;
@@ -2946,7 +2946,7 @@ tx_xmit_pkts(struct ice_tx_queue *txq,
                txq->tx_tail = 0;
 
        /* Update the tx tail register */
-       ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
+       ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
 
        return nb_pkts;
 }
index 5969a30..b72a9e7 100644 (file)
@@ -129,7 +129,7 @@ ice_rxq_rearm(struct ice_rx_queue *rxq)
                             (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 
        /* Update the tail pointer on the NIC */
-       ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
+       ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 }
 
 static inline __m256i
@@ -962,7 +962,7 @@ ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 
        txq->tx_tail = tx_id;
 
-       ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
+       ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
 
        return nb_pkts;
 }
index c4c9a91..1afd96a 100644 (file)
@@ -97,7 +97,7 @@ ice_rxq_rearm(struct ice_rx_queue *rxq)
                           (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 
        /* Update the tail pointer on the NIC */
-       ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
+       ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 }
 
 static inline void
@@ -689,7 +689,7 @@ ice_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 
        txq->tx_tail = tx_id;
 
-       ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
+       ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
 
        return nb_pkts;
 }