net/ice/base: add IEEE 1588 capability probing

Parse 1588 timesync capability during device capability probing.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 861f5a3..8fc0340 100644 (file)
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -108,6 +108,7 @@ struct ice_aqc_list_caps_elem {
 #define ICE_AQC_CAPS_TXQS                              0x0042
 #define ICE_AQC_CAPS_MSIX                              0x0043
 #define ICE_AQC_CAPS_FD                                        0x0045
+#define ICE_AQC_CAPS_1588                              0x0046
 #define ICE_AQC_CAPS_MAX_MTU                           0x0047
 #define ICE_AQC_CAPS_IWARP                             0x0051
 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE              0x0076

diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 51fca7b..185b900 100644 (file)
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2086,6 +2086,60 @@ ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
                  func_p->guar_num_vsi);
 }
 
+/**
+ * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for ICE_AQC_CAPS_1588.
+ */
+static void
+ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+                        struct ice_aqc_list_caps_elem *cap)
+{
+       struct ice_ts_func_info *info = &func_p->ts_func_info;
+       u32 number = LE32_TO_CPU(cap->number);
+
+       info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
+       func_p->common_cap.ieee_1588 = info->ena;
+
+       info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
+       info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
+       info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
+       info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
+
+       info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
+       info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
+
+       if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
+               info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
+       } else {
+               /* Unknown clock frequency, so assume a (probably incorrect)
+                * default to avoid out-of-bounds look ups of frequency
+                * related information.
+                */
+               ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
+                         info->clk_freq);
+               info->time_ref = ICE_TIME_REF_FREQ_25_000;
+       }
+
+       ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
+                 func_p->common_cap.ieee_1588);
+       ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
+                 info->src_tmr_owned);
+       ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
+                 info->tmr_ena);
+       ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
+                 info->tmr_index_owned);
+       ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
+                 info->tmr_index_assoc);
+       ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
+                 info->clk_freq);
+       ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
+                 info->clk_src);
+}
+
 /**
  * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
  * @hw: pointer to the HW struct
@@ -2151,6 +2205,9 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
                case ICE_AQC_CAPS_VSI:
                        ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
                        break;
+               case ICE_AQC_CAPS_1588:
+                       ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
+                       break;
                case ICE_AQC_CAPS_FD:
                        ice_parse_fdir_func_caps(hw, func_p);
                        break;
@@ -2204,6 +2261,57 @@ ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
                  dev_p->num_vsi_allocd_to_host);
 }
 
+/**
+ * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_1588 for device capabilities.
+ */
+static void
+ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+                       struct ice_aqc_list_caps_elem *cap)
+{
+       struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
+       u32 logical_id = LE32_TO_CPU(cap->logical_id);
+       u32 phys_id = LE32_TO_CPU(cap->phys_id);
+       u32 number = LE32_TO_CPU(cap->number);
+
+       info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
+       dev_p->common_cap.ieee_1588 = info->ena;
+
+       info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
+       info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
+       info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
+
+       info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
+       info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
+       info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
+
+       info->ena_ports = logical_id;
+       info->tmr_own_map = phys_id;
+
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
+                 dev_p->common_cap.ieee_1588);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
+                 info->tmr0_owner);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
+                 info->tmr0_owned);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
+                 info->tmr0_ena);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
+                 info->tmr1_owner);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
+                 info->tmr1_owned);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
+                 info->tmr1_ena);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
+                 info->ena_ports);
+       ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
+                 info->tmr_own_map);
+}
+
 /**
  * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
  * @hw: pointer to the HW struct
@@ -2262,6 +2370,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
                case ICE_AQC_CAPS_VSI:
                        ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
                        break;
+               case ICE_AQC_CAPS_1588:
+                       ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
+                       break;
                case  ICE_AQC_CAPS_FD:
                        ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
                        break;

diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2644d5d..daf1ac6 100644 (file)
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -439,6 +439,7 @@ struct ice_hw_common_caps {
 
        u8 dcb;
        u8 iscsi;
+       u8 ieee_1588;
        u8 mgmt_cem;
 
        /* WoL and APM support */
@@ -469,12 +470,82 @@ struct ice_hw_common_caps {
 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN   BIT(1)
 };
 
+/* IEEE 1588 TIME_SYNC specific info */
+/* Function specific definitions */
+#define ICE_TS_FUNC_ENA_M              BIT(0)
+#define ICE_TS_SRC_TMR_OWND_M          BIT(1)
+#define ICE_TS_TMR_ENA_M               BIT(2)
+#define ICE_TS_TMR_IDX_OWND_S          4
+#define ICE_TS_TMR_IDX_OWND_M          BIT(4)
+#define ICE_TS_CLK_FREQ_S              16
+#define ICE_TS_CLK_FREQ_M              MAKEMASK(0x7, ICE_TS_CLK_FREQ_S)
+#define ICE_TS_CLK_SRC_S               20
+#define ICE_TS_CLK_SRC_M               BIT(20)
+#define ICE_TS_TMR_IDX_ASSOC_S         24
+#define ICE_TS_TMR_IDX_ASSOC_M         BIT(24)
+
+/* TIME_REF clock rate specification */
+enum ice_time_ref_freq {
+       ICE_TIME_REF_FREQ_25_000        = 0,
+       ICE_TIME_REF_FREQ_122_880       = 1,
+       ICE_TIME_REF_FREQ_125_000       = 2,
+       ICE_TIME_REF_FREQ_153_600       = 3,
+       ICE_TIME_REF_FREQ_156_250       = 4,
+       ICE_TIME_REF_FREQ_245_760       = 5,
+
+       NUM_ICE_TIME_REF_FREQ
+};
+
+/* Clock source specification */
+enum ice_clk_src {
+       ICE_CLK_SRC_TCX0        = 0, /* Temperature compensated oscillator  */
+       ICE_CLK_SRC_TIME_REF    = 1, /* Use TIME_REF reference clock */
+
+       NUM_ICE_CLK_SRC
+};
+
+struct ice_ts_func_info {
+       /* Function specific info */
+       enum ice_time_ref_freq time_ref;
+       u8 clk_freq;
+       u8 clk_src;
+       u8 tmr_index_assoc;
+       u8 ena;
+       u8 tmr_index_owned;
+       u8 src_tmr_owned;
+       u8 tmr_ena;
+};
+
+/* Device specific definitions */
+#define ICE_TS_TMR0_OWNR_M             0x7
+#define ICE_TS_TMR0_OWND_M             BIT(3)
+#define ICE_TS_TMR1_OWNR_S             4
+#define ICE_TS_TMR1_OWNR_M             MAKEMASK(0x7, ICE_TS_TMR1_OWNR_S)
+#define ICE_TS_TMR1_OWND_M             BIT(7)
+#define ICE_TS_DEV_ENA_M               BIT(24)
+#define ICE_TS_TMR0_ENA_M              BIT(25)
+#define ICE_TS_TMR1_ENA_M              BIT(26)
+
+struct ice_ts_dev_info {
+       /* Device specific info */
+       u32 ena_ports;
+       u32 tmr_own_map;
+       u32 tmr0_owner;
+       u32 tmr1_owner;
+       u8 tmr0_owned;
+       u8 tmr1_owned;
+       u8 ena;
+       u8 tmr0_ena;
+       u8 tmr1_ena;
+};
+
 /* Function specific capabilities */
 struct ice_hw_func_caps {
        struct ice_hw_common_caps common_cap;
        u32 guar_num_vsi;
        u32 fd_fltr_guar;               /* Number of filters guaranteed */
        u32 fd_fltr_best_effort;        /* Number of best effort filters */
+       struct ice_ts_func_info ts_func_info;
 };
 
 /* Device wide capabilities */
@@ -482,6 +553,7 @@ struct ice_hw_dev_caps {
        struct ice_hw_common_caps common_cap;
        u32 num_vsi_allocd_to_host;     /* Excluding EMP VSI */
        u32 num_flow_director_fltr;     /* Number of FD filters available */
+       struct ice_ts_dev_info ts_dev_info;
        u32 num_funcs;
 };