net/mlx5: query software parsing support on Windows

Query software parsing supported on the NIC.

Save the offloads values in a config parameter.
This is needed for the outer IPv4 checksum and
IP and UDP tunneled packet TSO support.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Idan Hackmon <idanhac@nvidia.com>

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 122d4c9..859637f 100644 (file)
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -953,6 +953,22 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
        prf->obj = NULL;
 }
 
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
+{
+       uint32_t sw_parsing_offloads = 0;
+
+       if (attr->swp) {
+               sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
+               if (attr->swp_csum)
+                       sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
+
+               if (attr->swp_lso)
+                       sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
+       }
+       return sw_parsing_offloads;
+}
+
 /*
  * Allocate Rx and Tx UARs in robust fashion.
  * This routine handles the following UAR allocation issues:

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index d74ac19..483bf35 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1829,5 +1829,7 @@ int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
                             struct rte_flow_action_conntrack *profile);
 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
                          struct mlx5_aso_ct_action *ct);
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
 
 #endif /* RTE_PMD_MLX5_H_ */

diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index ba4f485..fefc648 100644 (file)
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -169,6 +169,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
                device_attr->max_rwq_indirection_table_size =
                        1 << hca_attr.rss_ind_tbl_cap;
        }
+       device_attr->sw_parsing_offloads =
+               mlx5_get_supported_sw_parsing_offloads(&hca_attr);
        pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
        if (pv_iseg == NULL) {
                DRV_LOG(ERR, "Failed to get device hca_iseg");
@@ -393,7 +395,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
        }
        DRV_LOG(DEBUG, "MPW isn't supported");
        mlx5_os_get_dev_attr(sh->ctx, &device_attr);
-       config->swp = 0;
+       config->swp = device_attr.sw_parsing_offloads &
+               (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+                MLX5_SW_PARSING_TSO_CAP);
        config->ind_table_max_size =
                sh->device_attr.max_rwq_indirection_table_size;
        cqe_comp = 0;

diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
index 7fe41d4..6de6833 100644 (file)
--- a/drivers/net/mlx5/windows/mlx5_os.h
+++ b/drivers/net/mlx5/windows/mlx5_os.h
@@ -16,4 +16,10 @@ enum {
 
 #define MLX5_NAMESIZE MLX5_FS_NAME_MAX
 
+enum mlx5_sw_parsing_offloads {
+       MLX5_SW_PARSING_CAP =      1 << 0,
+       MLX5_SW_PARSING_CSUM_CAP = 1 << 1,
+       MLX5_SW_PARSING_TSO_CAP =  1 << 2,
+};
+
 #endif /* RTE_PMD_MLX5_OS_H_ */