dpdk.git
4 years agodrivers: fix log type variables for -fno-common
Bruce Richardson [Fri, 10 Apr 2020 17:27:56 +0000 (18:27 +0100)]
drivers: fix log type variables for -fno-common

The zlib compression driver, as well as the aesni-gcm, aesni-mb and openssl
crypto drivers all defined the logtype variable in the header file
directly. This gives errors with gcc 10, due to -fno-common being the
default, so we need to apply the same fix in all cases:
* move the variable definition to a suitable .c file
* mark the forward declaration of the variable in the header as "extern"

Fixes: 0c4e4c16b004 ("compress/zlib: introduce zlib PMD")
Fixes: 90c8a2d02a31 ("crypto/aesni_gcm: add dynamic logging")
Fixes: 276624ae2ef6 ("crypto/aesni_mb: add dynamic logging")
Fixes: 094b2386f461 ("crypto/openssl: add dynamic logging")
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Lukasz Wojciechowski <l.wojciechow@partner.samsung.com>
4 years agoexamples/ipsec-secgw: support 192/256 AES key sizes
Anoob Joseph [Tue, 7 Apr 2020 06:30:42 +0000 (12:00 +0530)]
examples/ipsec-secgw: support 192/256 AES key sizes

Adding support for the following,
1. AES-192-GCM
2. AES-256-GCM
3. AES-192-CBC

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agocrypto/dpaa2_sec: remove unnecessary check
Yunjian Wang [Tue, 31 Mar 2020 10:22:48 +0000 (18:22 +0800)]
crypto/dpaa2_sec: remove unnecessary check

This NULL check is unnecessary, container_of is never NULL.

Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoeal/windows: fix build
Tal Shnaiderman [Tue, 21 Apr 2020 15:05:20 +0000 (18:05 +0300)]
eal/windows: fix build

Windows headers pthread.h and fnmatch.h
use rte_common types.

The error is: error: unknown type name '__rte_unused'

The fix adds the missing includes.

Bugzilla ID: 458
Fixes: f2fc83b40f06 ("replace unused attributes")

Signed-off-by: Tal Shnaiderman <talshn@mellanox.com>
4 years agoeal/windows: do not expose private facilities
Dmitry Kozlyuk [Tue, 14 Apr 2020 19:44:17 +0000 (22:44 +0300)]
eal/windows: do not expose private facilities

The goal of rte_os.h is to mitigate OS differences for EAL users.
In Windows EAL, rte_os.h did excessive things:

1. It included platform SDK headers (windows.h, etc). Those files are
   huge, require specific inclusion order, and are generally unused by
   the code including rte_os.h. Declarations from platform SDK may
   break otherwise platform-independent code, e.g. min, max, ERROR.

2. It included pthread.h, which is clearly not always required.

3. It defined functions private to Windows EAL.

Reorganize Windows EAL includes in the following way:

1. Create rte_windows.h to properly import Windows-specific facilities.
   Primary users are bus drivers, tests, and external applications.

2. Remove platform SDK includes from rte_os.h to prevent breaking
   otherwise portable code by including rte_os.h on Windows.
   Copy necessary definitions to avoid including those headers.

3. Remove pthread.h include from rte_os.h.

4. Move declarations private to Windows EAL into eal_windows.h.

Fixes: 428eb983f5f7 ("eal: add OS specific header file")

Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
4 years agovfio: fix use after free with multiprocess
Wei Hu (Xavier) [Tue, 21 Apr 2020 03:29:57 +0000 (11:29 +0800)]
vfio: fix use after free with multiprocess

This patch fixes the heap-use-after-free bug which was found by ASAN
(Address-Sanitizer) in the vfio_get_default_container_fd function.

Fixes: 6bcb7c95fe14 ("vfio: share default container in multi-process")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
4 years agovfio: fix race condition with sysfs
Michael Haeuptle [Mon, 6 Apr 2020 22:23:23 +0000 (22:23 +0000)]
vfio: fix race condition with sysfs

This fix treats a 0 return value from vfio_open_group_fd
in vfio_get_group_fd as the intended error condition instead
of putting an incorrect 0 file descriptor in the vfio_group table.

Sometimes, the creation of device files in sysfs is not
instantaneously causing vfio_open_groupfd to return 0.
This has been observed when hot removing/adding multiple
NVMe devices (>=4).

Fixes: 340b7bb8d583 ("vfio: extend data structure for multi container")
Cc: stable@dpdk.org
Signed-off-by: Michael Haeuptle <michael.haeuptle@hpe.com>
Acked-by: Darek Stojaczyk <dariusz.stojaczyk@intel.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
4 years agoeal: fix PRNG init with HPET enabled
Tonghao Zhang [Wed, 15 Apr 2020 17:41:06 +0000 (01:41 +0800)]
eal: fix PRNG init with HPET enabled

When rte_rand_init is invoked, and the kernel running dpdk does not
support *getentropy, at the same time, the cpu does not support rdseed,
then rte_rand_init invoked rte_get_timer_cycles.

If HPET was enabled in the DPDK build (CONFIG_RTE_LIBEAL_USE_HPET=y) and
the system, rte_get_timer_cycles will invoke rte_get_hpet_cycles while
*eal_hpet is not available.

To fix that, use rte_get_tsc_cycles instead of rte_get_timer_cycles.

Fixes: 3f002f069612 ("eal: replace libc-based random generation with LFSR")
Cc: stable@dpdk.org
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Acked-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoeal/ppc64: use glibc for cpu cycles count
Thinh Tran [Wed, 25 Mar 2020 00:13:56 +0000 (20:13 -0400)]
eal/ppc64: use glibc for cpu cycles count

__ppc_get_timebase() reads and returns the current value of the Time
Base Register. It's more efficient as it uses the processor’s time
base facility directly.

DPDK on FreeBSD currently is not supported on Powerpc64, it should
be safe to include the sys/platform/ppc.h.

Signed-off-by: Thinh Tran <thinhtr@linux.vnet.ibm.com>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
4 years agotest/malloc: add bad parameter tests for realloc
Anatoly Burakov [Thu, 2 Apr 2020 09:02:15 +0000 (10:02 +0100)]
test/malloc: add bad parameter tests for realloc

Realloc did not have bad parameter autotest. Add them.

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
4 years agotest/malloc: run realloc tests on external heap
Anatoly Burakov [Thu, 2 Apr 2020 09:02:14 +0000 (10:02 +0100)]
test/malloc: run realloc tests on external heap

Due to the fact that the rte_realloc() test depends on the layout of
underlying memory, it can sometimes fail due to fragmentation of the
memory. To address this, make it so that the realloc autotests are run
using a newly created external memory heap instead of main memory.

Bugzilla ID: 424

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Tested-by: David Christensen <drc@linux.vnet.ibm.com>
4 years agotest/ring: add functional tests for new sync modes
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:30 +0000 (13:28 +0100)]
test/ring: add functional tests for new sync modes

Extend test_ring_autotest with new test-cases for RTS/HTS sync modes.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agotest/ring: add stress test for MT peek API
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:29 +0000 (13:28 +0100)]
test/ring: add stress test for MT peek API

Introduce new test case to test MT peek API.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agoring: introduce peek style API
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:28 +0000 (13:28 +0100)]
ring: introduce peek style API

For rings with producer/consumer in RTE_RING_SYNC_ST, RTE_RING_SYNC_MT_HTS
mode, provide an ability to split enqueue/dequeue operation
into two phases:
      - enqueue/dequeue start
      - enqueue/dequeue finish
That allows user to inspect objects in the ring without removing
them from it (aka MT safe peek).

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agotest/ring: add contention stress test for HTS ring
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:27 +0000 (13:28 +0100)]
test/ring: add contention stress test for HTS ring

Introduce new test case to test HTS ring mode under contention.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agoring: introduce HTS ring mode
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:26 +0000 (13:28 +0100)]
ring: introduce HTS ring mode

Introduce head/tail sync mode for MT ring synchronization.
In that mode enqueue/dequeue operation is fully serialized:
only one thread at a time is allowed to perform given op.
Suppose to reduce stall times in case when ring is used on
overcommitted cpus (multiple active threads on the same cpu).

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agotest/ring: add contention stress test for RTS ring
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:25 +0000 (13:28 +0100)]
test/ring: add contention stress test for RTS ring

Introduce new test case to test RTS ring mode under contention.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agoring: introduce RTS ring mode
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:24 +0000 (13:28 +0100)]
ring: introduce RTS ring mode

Introduce relaxed tail sync (RTS) mode for MT ring synchronization.
Aim to reduce stall times in case when ring is used on
overcommited cpus (multiple active threads on the same cpu).
The main difference from original MP/MC algorithm is that
tail value is increased not by every thread that finished enqueue/dequeue,
but only by the last one.
That allows threads to avoid spinning on ring tail value,
leaving actual tail value change to the last thread in the update queue.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agoring: prepare ring to allow new sync schemes
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:23 +0000 (13:28 +0100)]
ring: prepare ring to allow new sync schemes

To make these preparations two main things are done:
- Change from *single* to *sync_type* to allow different
  synchronisation schemes to be applied.
  Mark *single* as deprecated in comments.
  Add new functions to allow user to query ring sync types.
  Replace direct access to *single* with appropriate function call.
- Move actual rte_ring and related structures definitions into a
  separate file: <rte_ring_core.h>. It allows to refer contents
  of <rte_ring_elem.h> from <rte_ring.h> without introducing a
  circular dependency.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agotest/ring: add contention stress test
Konstantin Ananyev [Mon, 20 Apr 2020 12:28:22 +0000 (13:28 +0100)]
test/ring: add contention stress test

Introduce stress test for ring enqueue/dequeue operations.
Performs the following pattern on each slave worker:
dequeue/read-write data from the dequeued objects/enqueue.
Serves as both functional and performance test of ring
enqueue/dequeue operations under high contention
(for both over committed and non-over committed scenarios).

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
4 years agobuild: add global libatomic dependency for 32-bit clang
Pavan Nikhilesh [Sun, 19 Apr 2020 10:01:01 +0000 (15:31 +0530)]
build: add global libatomic dependency for 32-bit clang

Add libatomic as a global dependency when compiling for 32-bit using
clang. As we need libatomic for 64-bit atomic ops.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
4 years agodevtools: skip ABI check in static builds
Thomas Monjalon [Tue, 21 Apr 2020 00:40:44 +0000 (02:40 +0200)]
devtools: skip ABI check in static builds

When running make with CONFIG_RTE_BUILD_SHARED_LIB=n,
no shared library is built.
In this case, no need to run ABI check.

With meson, both shared and static libraries are always built.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: David Marchand <david.marchand@redhat.com>
4 years agodevtools: reduce examples in static builds
Thomas Monjalon [Fri, 17 Apr 2020 22:16:56 +0000 (00:16 +0200)]
devtools: reduce examples in static builds

Static builds can take a lot of space, so reduce the number of examples
built when testing those static builds.

As makefile-based build is close to end of life, completely skip examples
in case of static linkage with make.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: David Marchand <david.marchand@redhat.com>
4 years agoci: reduce examples in static builds
Bruce Richardson [Mon, 16 Mar 2020 17:09:21 +0000 (17:09 +0000)]
ci: reduce examples in static builds

Static builds can take a lot of space, so reduce the number of examples
built when doing those static builds.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
4 years agoexamples/vm_power_manager: fix build
Ferruh Yigit [Fri, 17 Apr 2020 18:55:34 +0000 (19:55 +0100)]
examples/vm_power_manager: fix build

Build fails because '__rte_unused' macro not defined in file, error
produced by 'i686-native-linux-gcc config' but it seems generic issue.

Build error:
.../examples/vm_power_manager/oob_monitor_nop.c:11:13:
   error: expected ‘;’ before ‘static’
   11 | __rte_unused static float
      |             ^~~~~~~
      |             ;
.../examples/vm_power_manager/oob_monitor_nop.c:12:14:
   error: unknown type name ‘__rte_unused’
   12 | apply_policy(__rte_unused int core)
      |              ^~~~~~~~~~~~
.../examples/vm_power_manager/oob_monitor_nop.c:18:21:
   error: unknown type name ‘__rte_unused’
   18 | add_core_to_monitor(__rte_unused int core)
      |                     ^~~~~~~~~~~~
.../examples/vm_power_manager/oob_monitor_nop.c:24:26:
   error: unknown type name ‘__rte_unused’
   24 | remove_core_from_monitor(__rte_unused int core)
      |                          ^~~~~~~~~~~~

Including 'rte_common.h' header which defines the macro for fix.

Fixes: f2fc83b40f06 ("replace unused attributes")

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
4 years agoeal/ppc: fix build
David Marchand [Fri, 17 Apr 2020 14:56:11 +0000 (16:56 +0200)]
eal/ppc: fix build

Compilation is broken on ppc:

  CC otx2_rx.o
In file included from .../drivers/net/octeontx2/otx2_rx.c:5:0:
.../builds/ppc_64-power8-linux-gcc/include/rte_vect.h:29:17:
error: expected declaration specifiers or ‘...’ before numeric constant
 } __rte_aligned(16) rte_xmm_t;
                 ^~
compilation terminated due to -Wfatal-errors.

Fixes: f35e5b3e07b2 ("replace alignment attributes")

Signed-off-by: David Marchand <david.marchand@redhat.com>
Tested-by: Thomas Monjalon <thomas@monjalon.net>
4 years agodoc: remove similar columns from NIC features matrix
Thomas Monjalon [Wed, 11 Mar 2020 23:01:36 +0000 (00:01 +0100)]
doc: remove similar columns from NIC features matrix

The PMDs bnx2x and nfp have a separate column for VF.
Such separation is unneeded because the features are the same.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agodoc: remove empty columns from NIC features matrix
Thomas Monjalon [Wed, 11 Mar 2020 23:01:35 +0000 (00:01 +0100)]
doc: remove empty columns from NIC features matrix

The virtual PMDs bonding, KNI, null, ring, softnic and vdev_netvsc
have no real feature to advertise so they can be removed
from the (too) big matrix of ethdev features.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agodoc: fix matrix CSS for recent sphinx
Thomas Monjalon [Wed, 11 Mar 2020 23:01:34 +0000 (00:01 +0100)]
doc: fix matrix CSS for recent sphinx

It seems sphinx >= 2.0 is inserting a <p> tag in each table cell.
The feature table (matrix) style needs to be updated to avoid
cells being too big.

The margin, padding and line height are overridden.
The font size in percentage is replaced with an equivalent pixel size.
The border is explicit because it disappeared for th.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agolog: fix level picked with globbing on type register
Thomas Monjalon [Tue, 7 Apr 2020 22:47:58 +0000 (00:47 +0200)]
log: fix level picked with globbing on type register

When a log type is registered, the level can be picked
by matching saved options.
The check of fnmatch globbing result was reversed.

The same bug was already fixed in a similar function.
This one is acting in log type register function.

Note: this function rte_log_register_type_and_pick_level()
is not used a lot and could be merged with rte_log_register().

Fixes: 6ff0f81d0ef7 ("log: fix pattern matching")
Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agodevtools: check use of compiler attributes
Thomas Monjalon [Mon, 10 Feb 2020 16:00:32 +0000 (17:00 +0100)]
devtools: check use of compiler attributes

The keyword __attribute__ will emit a warning,
because it is preferred to use or define a common __rte macro.
The centralized macros may help to control or workaround some compilers.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace no-return attributes
Thomas Monjalon [Sun, 9 Feb 2020 20:24:18 +0000 (21:24 +0100)]
replace no-return attributes

The new macro __rte_noreturn, for compiler hinting,
is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace cold attributes
Thomas Monjalon [Sun, 9 Feb 2020 18:20:03 +0000 (19:20 +0100)]
replace cold attributes

The new macro __rte_cold, for compiler hinting,
is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
4 years agoreplace hot attributes
Thomas Monjalon [Sun, 9 Feb 2020 17:39:19 +0000 (18:39 +0100)]
replace hot attributes

The new macro __rte_hot, for compiler hinting,
is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace used attributes
Thomas Monjalon [Sun, 9 Feb 2020 19:43:11 +0000 (20:43 +0100)]
replace used attributes

The new macro __rte_used, forcing symbol to be generated,
is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace unused attributes
Thomas Monjalon [Sun, 9 Feb 2020 15:54:54 +0000 (16:54 +0100)]
replace unused attributes

There is a common macro __rte_unused, avoiding warnings,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace no-inline attributes
Thomas Monjalon [Sun, 9 Feb 2020 17:32:42 +0000 (18:32 +0100)]
replace no-inline attributes

There is a macro __rte_noinline, preventing function to be inlined,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace always-inline attributes
Thomas Monjalon [Sun, 9 Feb 2020 12:27:49 +0000 (13:27 +0100)]
replace always-inline attributes

There is a macro __rte_always_inline, forcing functions to be inlined,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace packed attributes
Thomas Monjalon [Sun, 9 Feb 2020 17:29:23 +0000 (18:29 +0100)]
replace packed attributes

There is a common macro __rte_packed for packing structs,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoreplace alignment attributes
Thomas Monjalon [Sun, 9 Feb 2020 12:16:42 +0000 (13:16 +0100)]
replace alignment attributes

There is a common macro __rte_aligned for alignment,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
4 years agocommon/mlx5: replace alignas keyword
Thomas Monjalon [Sun, 9 Feb 2020 12:00:22 +0000 (13:00 +0100)]
common/mlx5: replace alignas keyword

The keyword alignas can be replaced with __rte_aligned macro
for consistency and allow compilers compatibility control.

The macro __rte_cache_aligned is a shortcut including __rte_aligned
and RTE_CACHE_LINE_SIZE constant.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agonet/memif: use common macros for cache line marker
Thomas Monjalon [Sun, 9 Feb 2020 12:14:15 +0000 (13:14 +0100)]
net/memif: use common macros for cache line marker

The macros RTE_MARKER and __rte_cache_aligned can be used
for consistency for describing MEMIF_CACHELINE_ALIGN_MARK.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agonet/mlx5: replace destructor syntax with common macro
Thomas Monjalon [Sun, 9 Feb 2020 20:33:29 +0000 (21:33 +0100)]
net/mlx5: replace destructor syntax with common macro

There is a macro RTE_FINI for destructors,
which is now used where appropriate for consistency.

The destructor function mlx5_pmd_socket_uninit does not need
to be declared separately in mlx5.h.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agoipsec: fix build dependency on hash lib
Akhil Goyal [Thu, 16 Apr 2020 11:25:17 +0000 (16:55 +0530)]
ipsec: fix build dependency on hash lib

rte_ipsec has a dependency on rte_hash
So we need the librte_hash to be compiled before librte_ipsec.
Add the DEPDIRs to make sure this.

Fixes: 3feb23609cae ("ipsec: add SAD create/destroy implementation")
Cc: stable@dpdk.org
Reported-by: Raslan Darawsheh <rasland@mellanox.com>
Suggested-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoevent/dsw: fix gcc 4.8 false positive warning
Mattias Rönnblom [Wed, 15 Apr 2020 18:15:37 +0000 (20:15 +0200)]
event/dsw: fix gcc 4.8 false positive warning

Add redundant stack variable initialization to work around
false-positive warnings in older versions of GCC.

Fixes: 1f2b99e8d9b1 ("event/dsw: improve migration mechanism")

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agomaintainers: update for Marvell OCTEON TX2
Jerin Jacob [Wed, 15 Apr 2020 14:52:44 +0000 (20:22 +0530)]
maintainers: update for Marvell OCTEON TX2

Vamsi is no longer associated with Marvell.
Updating Marvell OCTEON TX2 PMDs MAINTAINERS file.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
4 years agobitmap: add init with all bits set
Suanming Mou [Fri, 10 Apr 2020 12:46:26 +0000 (20:46 +0800)]
bitmap: add init with all bits set

Currently, in the case to use bitmap as resource allocator, after
bitmap creation, all the bitmap bits should be set to indicate the
bit available. Every time when allocate one bit, search for the set
bits and clear it to make it in use.

Add a new rte_bitmap_init_with_all_set() function to have a quick
fill up the bitmap bits.

Comparing with the case create the bitmap as empty and set the bitmap
one by one, the new function costs less cycles.

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
4 years agotest: remove meson dependency on /proc file
Thomas Monjalon [Thu, 9 Apr 2020 16:41:49 +0000 (18:41 +0200)]
test: remove meson dependency on /proc file

Meson is detecting the path /proc/sys/vm/nr_hugepages in the call to cat
in app/test/meson.build and then adding it as a build dependency.
This causes build loop if the timestamp of this file keeps changing.

It is fixed by hiding hugepage check in a shell script.

Fixes: 77784ef0fba8 ("test: allow no-huge mode for fast-tests")

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Tested-by: Lukasz Wojciechowski <l.wojciechow@partner.samsung.com>
Reviewed-by: Lukasz Wojciechowski <l.wojciechow@partner.samsung.com>
Acked-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
4 years agodoc: fix sphinx compatibility
Thomas Monjalon [Wed, 8 Apr 2020 08:09:23 +0000 (10:09 +0200)]
doc: fix sphinx compatibility

The function add_stylesheet() is deprecated since sphinx 1.8.
It will be removed in sphinx 4.0.
It is replaced by add_css_file().

Cc: stable@dpdk.org
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agomaintainers: update for rawdev
Hemant Agrawal [Mon, 30 Mar 2020 05:17:29 +0000 (10:47 +0530)]
maintainers: update for rawdev

Replace rawdev maintainer. Shreyansh is no longer with NXP.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Nipun Gupta <nipun.gupta@nxp.com>
4 years agomaintainers: update for Marvell ARMADA
Liron Himi [Mon, 30 Mar 2020 08:01:32 +0000 (11:01 +0300)]
maintainers: update for Marvell ARMADA

update MRVL PMDs, Tomasz is no longer with semihalf

Signed-off-by: Liron Himi <lironh@marvell.com>
4 years agoevent/octeontx2: use C11 atomics for statistics
Pavan Nikhilesh [Fri, 27 Mar 2020 08:55:58 +0000 (14:25 +0530)]
event/octeontx2: use C11 atomics for statistics

Use c11 atomics with RELAXED ordering instead of rte_atomic ops which
enforce unnessary barriers on arm64.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
4 years agoexamples/l2fwd-event: add option to configure port pairs
Pavan Nikhilesh [Tue, 31 Mar 2020 12:53:15 +0000 (18:23 +0530)]
examples/l2fwd-event: add option to configure port pairs

Current l2fwd-event application statically configures adjacent ports as
destination ports for forwarding the traffic.

Add a config option to pass the forwarding port pair mapping which allows
the user to configure forwarding port mapping.

If no config argument is specified, destination port map is not
changed and traffic gets forwarded with existing mapping.

To align port/queue configuration of each lcore with destination port
map, port/queue configuration of each lcore gets modified when config
option is specified.

Ex: ./l2fwd-event -c 0xff -- -p 0x3f -q 2 --config="(0,3)(1,4)(2,5)"

With above config option, traffic received from portid = 0 gets forwarded
to port = 3 and vice versa, similarly traffic gets forwarded on other port
pairs (1,4) and (2,5).

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Andrzej Ostruszka <aostruszka@marvell.com>
4 years agoapp/eventdev: validate producer type
Pavan Nikhilesh [Thu, 2 Apr 2020 19:38:07 +0000 (01:08 +0530)]
app/eventdev: validate producer type

Validate the producer type used for pipeline and order test suites.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
4 years agoevent/dsw: add port busy cycles xstats
Mattias Rönnblom [Mon, 9 Mar 2020 06:51:06 +0000 (07:51 +0100)]
event/dsw: add port busy cycles xstats

DSW keeps an internal port load estimate, used by the load balancing
mechanism. As a side effect, it keeps track of the total number of
busy cycles since startup. This metric is indirectly exposed in the
form of DSW xstats' "port_<n>_event_proc_latency", which is the total
number of busy cycles divided by the total number of events processed
on a particular port.

An external application can take (event_latency * dequeued) to go back
to busy_cycles. One reason for doing this is to measure the port's
load during a longer time period, without resorting to sampling
"port_<n>_load". However, as the number dequeued events grows, a
rounding error in event_latency renders the application-calculated
busy_cycles inaccurate.

Thus, it makes sense to directly expose the number of busy cycles as a
DSW xstats, even though it might seem redundant.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: remove unnecessary read barrier
Mattias Rönnblom [Mon, 9 Mar 2020 06:51:05 +0000 (07:51 +0100)]
event/dsw: remove unnecessary read barrier

Remove unnecessary read barrier (and misleading comment) on control
message dequeue.

Fixes: f6257b22e767 ("event/dsw: add load balancing")
Cc: stable@dpdk.org
Suggested-by: Ola Liljedahl <ola.liljedahl@arm.com>
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: remove redundant control ring poll
Mattias Rönnblom [Mon, 9 Mar 2020 06:51:04 +0000 (07:51 +0100)]
event/dsw: remove redundant control ring poll

On dequeue, polling the control ring once is enough.

Fixes: f6257b22e767 ("event/dsw: add load balancing")
Cc: stable@dpdk.org
Suggested-by: Ola Liljedahl <ola.liljedahl@arm.com>
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: avoid migration waves in large systems
Mattias Rönnblom [Mon, 9 Mar 2020 06:51:03 +0000 (07:51 +0100)]
event/dsw: avoid migration waves in large systems

DSW limits the rate of migrations on a per-port basis. Hence, as the
number of cores grows, so does the total migration capacity.

In high core-count systems, this allows for a situation where flows
are migrated to a lightly loaded port which recently already received
a number of new flows (from other ports). The processing load
generated by these new flows may not yet be reflected in the lightly
loaded port's load estimate. The result is that the previously lightly
loaded port is now overloaded.

This patch adds a rough estimate of the size of the inbound migrations
to a particular port, which can be factored into the migration logic,
avoiding the above problem.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: improve migration mechanism
Mattias Rönnblom [Mon, 9 Mar 2020 06:51:02 +0000 (07:51 +0100)]
event/dsw: improve migration mechanism

Allowing moving multiple flows in one migration transaction, to
rebalance load more quickly.

Introduce a threshold to avoid migrating flows between ports with very
similar load.

Simplify logic for selecting which flow to migrate. The aim is now to
move flows in such a way that the receiving port is as lightly-loaded
as possible (after receiving the flow), while still migrating enough
flows from the source port to reduce its load. This is essentially how
legacy strategy work as well, but the code is more readable.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: extend xstats
Mattias Rönnblom [Sat, 4 Apr 2020 12:45:26 +0000 (18:15 +0530)]
event/dsw: extend xstats

To allow visualization of migrations, track the number flow
immigrations in "port_<N>_immigrations". The "port_<N>_migrations"
retains legacy semantics, but is renamed "port_<N>_emigrations".

Expose the number of events currently undergoing processing
(i.e. pending releases) at a particular port.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: reduce max flows to speed up load balancing
Mattias Rönnblom [Mon, 9 Mar 2020 06:51:00 +0000 (07:51 +0100)]
event/dsw: reduce max flows to speed up load balancing

Reduce the maximum number of DSW flows from 32k to 8k, to be able
rebalance load faster.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/dsw: reduce latency in low-load situations
Mattias Rönnblom [Mon, 9 Mar 2020 06:50:59 +0000 (07:50 +0100)]
event/dsw: reduce latency in low-load situations

In DSW, in case a port can't produce any events for the application to
consume, the port is considered idle.

To slightly reduce wall-time latency, flush the port's output buffer
in case of such an empty dequeue.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
4 years agoevent/octeontx2: remove WFE from dual-slot dequeue
Pavan Nikhilesh [Fri, 14 Feb 2020 06:45:24 +0000 (12:15 +0530)]
event/octeontx2: remove WFE from dual-slot dequeue

Each workslot is always bound to a specific lcore there is no multi-core
contention to cause cache trashing as a result it is safe to remove the
WFE. Also, in dual workslot dequeue work will mostlikely be available on
the pair workslot making WFE impractical.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
4 years agobuild: disable experimental API check internally
Pavan Nikhilesh [Mon, 13 Apr 2020 14:55:30 +0000 (16:55 +0200)]
build: disable experimental API check internally

Remove setting ALLOW_EXPERIMENTAL_API individually for each Makefile and
meson.build. Instead, enable ALLOW_EXPERIMENTAL_API flag across app, lib
and drivers.
This changes reduces the clutter across the project while still
maintaining the functionality of ALLOW_EXPERIMENTAL_API i.e. warning
external applications about experimental API usage.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
4 years agocrypto/nitrox: support 3DES-CBC
Nagadheeraj Rottela [Fri, 13 Mar 2020 11:43:37 +0000 (17:13 +0530)]
crypto/nitrox: support 3DES-CBC

This patch adds 3DES CBC mode cipher algorithm.

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
4 years agoexamples/ipsec-secgw: enable CPU crypto fallback
Mariusz Drost [Wed, 18 Mar 2020 13:26:59 +0000 (14:26 +0100)]
examples/ipsec-secgw: enable CPU crypto fallback

Added cpu-crypto fallback option parsing as well as tests for it

Signed-off-by: Mariusz Drost <mariuszx.drost@intel.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
4 years agocrypto/nitrox: fix oversized device name
Nagadheeraj Rottela [Fri, 27 Mar 2020 13:42:39 +0000 (19:12 +0530)]
crypto/nitrox: fix oversized device name

In nitrox_sym_pmd_create() the name array will overflow if the pci
device name is greater than 57 bytes. To fix this issue subtract pci
device name length from array length while appending substring to the
name.

Coverity issue: 349926
Fixes: 9fdef0cc2385 ("crypto/nitrox: create symmetric cryptodev")
Cc: stable@dpdk.org
Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agocrypto/nitrox: fix CSR register address generation
Nagadheeraj Rottela [Fri, 27 Mar 2020 13:42:38 +0000 (19:12 +0530)]
crypto/nitrox: fix CSR register address generation

If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will
evaluate to incorrect values due to unintended sign extension from int
to unsigned long. To fix this, add UL suffix to the constants in these
macros. The same problem is with AQMQ_QSZX() macro also.

Coverity issue: 349899, 349905, 349911, 349921, 349923
Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")
Fixes: 0a8fc2423bff ("crypto/nitrox: introduce Nitrox driver")
Cc: stable@dpdk.org
Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agocrypto/qat: handle mixed hash-cipher on GEN2
Adam Dybkowski [Thu, 26 Mar 2020 16:22:08 +0000 (17:22 +0100)]
crypto/qat: handle mixed hash-cipher on GEN2

This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocommon/qat: get firmware version
Adam Dybkowski [Thu, 26 Mar 2020 16:22:07 +0000 (17:22 +0100)]
common/qat: get firmware version

This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agoapp/bbdev: update test vectors
Nicolas Chautru [Thu, 26 Mar 2020 03:27:48 +0000 (20:27 -0700)]
app/bbdev: update test vectors

Modification to vectors parameters used for unit test
for coverage and performance test of bbdev drivers
across all devices.
Updating and reducing list for focused coverage on relevant
code blocks for 4G and 5G. Less focus on 4G TB mode as there is
some question how to best support this with mbuf limitations and
if effect are not used.
Removing scenarios with negative LLR assumptions which are not
used with any PMDs and historical only.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoapp/bbdev: support offload test for LDPC
Nicolas Chautru [Thu, 26 Mar 2020 03:27:47 +0000 (20:27 -0700)]
app/bbdev: support offload test for LDPC

Adding support for the offload latency tests when
using the LDPC encoder and decoder operations.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoapp/bbdev: support LDPC interrupt test
Nicolas Chautru [Thu, 26 Mar 2020 03:27:46 +0000 (20:27 -0700)]
app/bbdev: support LDPC interrupt test

Adding missing implementation for the interrupt tests
for LDPC encoder and decoders.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoapp/bbdev: add performance tests
Nicolas Chautru [Thu, 26 Mar 2020 03:27:45 +0000 (20:27 -0700)]
app/bbdev: add performance tests

Includes support for BLER (Block Error Rate) wireless
performance test with new arguments for SNR and number
of iterations for 5G. This generates LLRs for a given
SNR level then measures the ratio of code blocks being
successfully decoded or not.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoapp/bbdev: support HARQ validation
Nicolas Chautru [Thu, 26 Mar 2020 03:27:44 +0000 (20:27 -0700)]
app/bbdev: support HARQ validation

Adding functionality to validate HARQ for different
devices implementation.
Adding capacity to fetch HARQ data when required as
part of this validation.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoapp/bbdev: rename FPGA LTE macros to be more explicit
Nicolas Chautru [Thu, 26 Mar 2020 03:27:43 +0000 (20:27 -0700)]
app/bbdev: rename FPGA LTE macros to be more explicit

Self-contained and cosmetic renaming of macro
so that to be more explicit for future extension.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agobaseband/turbo_sw: support large size code block
Nicolas Chautru [Thu, 26 Mar 2020 03:27:42 +0000 (20:27 -0700)]
baseband/turbo_sw: support large size code block

This is to support cases when the input data for
decoding a code block is larger than 64kB and would
not fit as a contiguous block of data into one
mbuf. In that case the length from the operation
supersedes the mbuf default structure.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agobaseband/turbo_sw: fix exposed LLR decimals assumption
Nicolas Chautru [Thu, 26 Mar 2020 03:27:41 +0000 (20:27 -0700)]
baseband/turbo_sw: fix exposed LLR decimals assumption

The actual LLR representation was incorrectly assumed to be 2
instead of 4. This would impact wireless performance but is not
critical to be back ported on LTS branches.

Fixes: c769c711757a ("baseband/turbo_sw: extend for 5G")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agobbdev: expose device HARQ buffer size at device level
Nicolas Chautru [Thu, 26 Mar 2020 03:27:40 +0000 (20:27 -0700)]
bbdev: expose device HARQ buffer size at device level

This exposes the HARQ buffer size at the device driver level
instead of using the capability of a specific operation.

This is currently not yet used by a device until
future commit.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agobbdev: add capability for filler bits inclusion in HARQ
Nicolas Chautru [Thu, 26 Mar 2020 03:27:39 +0000 (20:27 -0700)]
bbdev: add capability for filler bits inclusion in HARQ

Adding capability flag for device variants when HARQ buffer
may or may not include the filler bits.
Minor cosmetic changes in same file.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agotest/crypto: add AES-GCM J0 case
Arek Kusztal [Fri, 13 Mar 2020 18:07:51 +0000 (19:07 +0100)]
test/crypto: add AES-GCM J0 case

This patch adds crypto J0 test case to AES-GCM

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocrypto/qat: support AES-GCM J0
Arek Kusztal [Fri, 13 Mar 2020 18:07:50 +0000 (19:07 +0100)]
crypto/qat: support AES-GCM J0

This patch adds J0 capability to Intel QuickAssist Technology driver

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agotest/ipsec: fix crash in session destroy
Ruifeng Wang [Fri, 20 Mar 2020 08:05:20 +0000 (16:05 +0800)]
test/ipsec: fix crash in session destroy

Segfault was observed when running ipsec unit test:

 + TestCase [10] : test_ipsec_replay_inb_repeat_null_null_wrapper
                   succeeded
 + TestCase [11] : test_ipsec_replay_inb_inside_burst_null_null_wrapper
                   succeeded
 + TestCase [12] : test_ipsec_crypto_inb_burst_2sa_null_null_wrapper
                   succeeded
 + TestCase [13] : test_ipsec_crypto_inb_burst_2sa_4grp_null_null_wrapper
                   succeeded
Segmentation fault

Data corruption happens due to incorrect destroy of session. Security
session needs process different from crypto session.

Destroy corresponding sessions according to different security actions.

Fixes: 05fe65eb66b2 ("test/ipsec: introduce functional test")
Cc: stable@dpdk.org
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
4 years agocommon/qat: optimise calculation of cookie index
Fiona Trahe [Wed, 11 Mar 2020 12:26:08 +0000 (13:26 +0100)]
common/qat: optimise calculation of cookie index

Avoid costly division, use shift instead.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
4 years agocrypto/qat: optimise check for chained mbufs
Fiona Trahe [Wed, 11 Mar 2020 12:26:07 +0000 (13:26 +0100)]
crypto/qat: optimise check for chained mbufs

To detect if sgl, use nb_segs > 1, instead of checking for next pointer,
as nb_segs is in first cache-line while next is in second cache-line.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
4 years agocrypto/qat: improve out-of-place conditional check
Fiona Trahe [Wed, 11 Mar 2020 12:26:06 +0000 (13:26 +0100)]
crypto/qat: improve out-of-place conditional check

Improve case where application set m_dst to same as m_src
so really an in-place operation, though would have been treated
as out-of-place. No functional change but this path can now benefit
from DMA alignment.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
4 years agocompressdev: remove unused function pointer prototype
Artur Trybula [Fri, 6 Mar 2020 11:16:35 +0000 (12:16 +0100)]
compressdev: remove unused function pointer prototype

This commit removes unused prototype of the function pointer
compressdev_queue_pair_count_t.

Signed-off-by: Artur Trybula <arturx.trybula@intel.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
4 years agocryptodev: remove unused operation for queue count
Artur Trybula [Fri, 6 Mar 2020 11:16:33 +0000 (12:16 +0100)]
cryptodev: remove unused operation for queue count

This commit removes unused function pointer (queue_pair_count)
from struct rte_cryptodev_ops. Related functions removed as well.

Signed-off-by: Artur Trybula <arturx.trybula@intel.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
4 years agocommon/qat: fix GEN3 marketing name
Adam Dybkowski [Wed, 4 Mar 2020 13:18:35 +0000 (14:18 +0100)]
common/qat: fix GEN3 marketing name

This patch fixes the marketing name of the QAT GEN3 to P5xxx.
Updates this name mentioned in the compression PMD as well as
in the documentation.

Fixes: aa983f03ad2e ("crypto/qat: handle Single Pass Crypto Requests on GEN3")
Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
Fixes: 1f5e4053f9b4 ("common/qat: support GEN3 devices")
Cc: stable@dpdk.org
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocryptodev: fix missing device id range checking
Adam Dybkowski [Thu, 20 Feb 2020 15:04:15 +0000 (16:04 +0100)]
cryptodev: fix missing device id range checking

This patch adds range-checking of the device id passed from
the user app code. It prevents out-of-range array accesses
which in some situations resulted in an
application crash (segfault).

Fixes: 3dd4435cf473 ("cryptodev: fix checks related to device id")
Cc: stable@dpdk.org
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agotest/crypto: add AES-256 DOCSIS test vectors
Mairtin o Loingsigh [Wed, 26 Feb 2020 09:04:11 +0000 (09:04 +0000)]
test/crypto: add AES-256 DOCSIS test vectors

This patch adds test vectors for AES-256 and sets QAT as the
target PMD.

Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocrypto/qat: support DOCSIS AES-256
Mairtin o Loingsigh [Wed, 26 Feb 2020 09:04:10 +0000 (09:04 +0000)]
crypto/qat: support DOCSIS AES-256

This patch adds support for DOCSIS AES-256 when using qat

Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agoexamples/ipsec-secgw: reserve crypto queues in event mode
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:37 +0000 (17:18 +0100)]
examples/ipsec-secgw: reserve crypto queues in event mode

Reserve minimum number of crypto queues equal to number of ports.
This is to fulfill inline protocol offload requirements.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agodoc: add event mode to ipsec-secgw
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:36 +0000 (17:18 +0100)]
doc: add event mode to ipsec-secgw

Document addition of event mode support
to ipsec-secgw application.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoexamples/ipsec-secgw: make number of buffers dynamic
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:35 +0000 (17:18 +0100)]
examples/ipsec-secgw: make number of buffers dynamic

Make number of buffers in a pool nb_mbuf_in_pool dependent on number
of ports, cores and crypto queues. Add command line option -s which
when used overrides dynamic calculation of number of buffers in a pool.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoexamples/ipsec-secgw: add app mode worker
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:34 +0000 (17:18 +0100)]
examples/ipsec-secgw: add app mode worker

Add application inbound/outbound worker thread and
IPsec application processing code for event mode.

Example ipsec-secgw command in app mode:
ipsec-secgw -w 0002:02:00.0,ipsec_in_max_spi=128
-w 0002:03:00.0,ipsec_in_max_spi=128 -w 0002:0e:00.0 -w 0002:10:00.1
--log-level=8 -c 0x1 -- -P -p 0x3 -u 0x1 -f aes-gcm.cfg
--transfer-mode event --event-schedule-type parallel

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoexamples/ipsec-secgw: add driver mode worker
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:33 +0000 (17:18 +0100)]
examples/ipsec-secgw: add driver mode worker

Add driver inbound and outbound worker thread for ipsec-secgw. In driver
mode application does as little as possible. It simply forwards packets
back to port from which traffic was received instructing HW to apply
inline security processing using first outbound SA configured for
a given port. If a port does not have SA configured outbound traffic
on that port will be silently dropped. The aim of this mode is to
measure HW capabilities. Driver mode is selected with single-sa option.
The single-sa option accepts SA index however in event mode the SA
index is ignored.

Example command to run ipsec-secgw in driver mode:
ipsec-secgw -w 0002:02:00.0,ipsec_in_max_spi=128
-w 0002:03:00.0,ipsec_in_max_spi=128 -w 0002:0e:00.0 -w 0002:10:00.1
--log-level=8 -c 0x1 -- -P -p 0x3 -u 0x1 -f aes-gcm.cfg
--transfer-mode event --event-schedule-type parallel --single-sa 0

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoexamples/ipsec-secgw: add event mode
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:32 +0000 (17:18 +0100)]
examples/ipsec-secgw: add event mode

Add eventmode support to ipsec-secgw. With the aid of event helper
configure and use the eventmode capabilities.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoexamples/ipsec-secgw: add event helper config init/uninit
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:31 +0000 (17:18 +0100)]
examples/ipsec-secgw: add event helper config init/uninit

Add eventmode helper eh_conf_init and eh_conf_uninit
functions which purpose is to initialize and
uninitialize eventmode helper configuration.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoexamples/ipsec-secgw: support internal ports for events
Lukasz Bartosik [Thu, 27 Feb 2020 16:18:30 +0000 (17:18 +0100)]
examples/ipsec-secgw: support internal ports for events

Add support for Rx and Tx internal ports. When internal ports are
available then a packet can be received from eth port and forwarded
to event queue by HW without any software intervention. The same
applies to Tx side where a packet sent to an event queue can by
forwarded by HW to eth port without any software intervention.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>